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1. 发明公开

US20230281030A1 JUST IN TIME COMPILATION USING LINK TIME OPTIMIZATION 审中-公开
公开(公告)号：US20230281030A1
公开(公告)日：2023-09-07
申请号：US17688797
申请日：2022-03-07
申请人： NVIDIA Corporation
发明人： Michael Murphy , Shelton George Dsouza , Shandeep Nagori , Thibaut Lutz
IPC分类号： G06F9/455 , G06F9/445
CPC分类号： G06F9/4552 , G06F9/44521
摘要： A first intermediate representation of a first portion of a source code implementing an application and a second intermediate representation of a second portion of the source code is received by a processing device. The first intermediate representation and the second intermediate representation is merged, at run-time, into a merged intermediate representation, wherein the first intermediate representation includes a reference to a function in the second intermediate representation. An execution flow transfer instruction within the merged intermediate representation is identified based on a run-time value of a parameter of the application. The execution flow transfer instruction references the function. A set of executable instructions implementing the function is identified within the merged intermediate representation. The execution flow transfer instruction is replaced with a copy of the set of executable instructions implementing the function.

2. 发明授权

US09639336B2 Algorithm for vectorization and memory coalescing during compiling 有权
公开(公告)号：US09639336B2
公开(公告)日：2017-05-02
申请号：US13660986
申请日：2012-10-25
申请人： NVIDIA Corporation
发明人： Vinod Grover , Manjunath Kudlur , Michael Murphy
IPC分类号： G06F9/44 , G06F9/45 , G06F9/50
CPC分类号： G06F8/443 , G06F8/41 , G06F8/433 , G06F8/4442 , G06F8/445 , G06F8/45 , G06F8/456 , G06F9/5066
摘要： One embodiment of the present invention sets forth a technique for reducing the number of assembly instructions included in a computer program. The technique involves receiving a directed acyclic graph (DAG) that includes a plurality of nodes, where each node includes an assembly instruction of the computer program, hierarchically parsing the plurality of nodes to identify at least two assembly instructions that are vectorizable and can be replaced by a single vectorized assembly instruction, and replacing the at least two assembly instructions with the single vectorized assembly instruction.

3. 发明公开

US20240095044A1 APPLICATION PROGRAMMING INTERFACE TO MODIFY CODE 审中-公开
公开(公告)号：US20240095044A1
公开(公告)日：2024-03-21
申请号：US17749936
申请日：2022-05-20
申请人： NVIDIA Corporation
发明人： Shelton George Dsouza , Michael Murphy
IPC分类号： G06F9/445 , G06F8/51 , G06F9/54
CPC分类号： G06F9/44521 , G06F8/51 , G06F9/547
摘要： Apparatuses, systems, and techniques to optimize processor performance. In at least one embodiment, a processor is to perform an application programming interface (API) to exclude one or more portions of program code from a program.

4. 发明公开

US20230376287A1 CODE GENERATION TECHNIQUE 审中-公开
公开(公告)号：US20230376287A1
公开(公告)日：2023-11-23
申请号：US17749925
申请日：2022-05-20
申请人： NVIDIA Corporation
发明人： Shelton George Dsouza , Michael Murphy
IPC分类号： G06F8/40
CPC分类号： G06F8/40
摘要： Apparatuses, systems, and techniques to optimize processor performance. In at least one embodiment, a method optimizes linked code based, at least in part, on storing an indication of whether two portions of code have been linked.

5. 发明申请

US20190171466A1 METHOD AND SYSTEM FOR MULTIPLE EMBEDDED DEVICE LINKS IN A HOST EXECUTABLE 审中-公开
公开(公告)号：US20190171466A1
公开(公告)日：2019-06-06
申请号：US16268106
申请日：2019-02-05
申请人： Nvidia Corporation
发明人： Jaydeep Marathe , Michael Murphy , Sean Y. Lee
IPC分类号： G06F9/445 , G06F8/41 , G06F8/54
摘要： Embodiments of the present invention provide a novel solution to generate multiple linked device code portions within a final executable file. Embodiments of the present invention are operable to extract device code from their respective host object filesets and then link them together to form multiple linked device code portions. Also, using the identification process described by embodiments of the present invention, device code embedded within host objects may also be uniquely identified and linked in accordance with the protocols of conventional programming languages. Furthermore, these multiple linked device code portions may be then converted into distinct executable forms of code that may be encapsulated within a single executable file.

6. 发明授权

US10261807B2 Method and system for multiple embedded device links in a host executable 有权
公开(公告)号：US10261807B2
公开(公告)日：2019-04-16
申请号：US13850237
申请日：2013-03-25
申请人： NVIDIA Corporation
发明人： Jaydeep Marathe , Michael Murphy , Sean Y. Lee
IPC分类号： G06F8/41 , G06F9/445 , G06F8/54
摘要： Embodiments of the present invention provide a novel solution to generate multiple linked device code portions within a final executable file. Embodiments of the present invention are operable to extract device code from their respective host object filesets and then link them together to form multiple linked device code portions. Also, using the identification process described by embodiments of the present invention, device code embedded within host objects may also be uniquely identified and linked in accordance with the protocols of conventional programming languages. Furthermore, these multiple linked device code portions may be then converted into distinct executable forms of code that may be encapsulated within a single executable file.

7. 发明授权

US09483235B2 Method and system for separate compilation of device code embedded in host code 有权
标题翻译：用于单独编译嵌入在主机代码中的设备代码的方法和系统
公开(公告)号：US09483235B2
公开(公告)日：2016-11-01
申请号：US13850207
申请日：2013-03-25
申请人： NVIDIA Corporation
发明人： Michael Murphy , Sean Y. Lee , Stephen Jones , Girish Bharambe , Jaydeep Marathe
IPC分类号： G06F9/45 , G06F9/44 , G06F9/445
CPC分类号： G06F8/30 , G06F8/41 , G06F8/54
摘要： Embodiments of the present invention provide a novel solution that supports the separate compilation of host code and device code used within a heterogeneous programming environment. Embodiments of the present invention are operable to link device code embedded within multiple host object files using a separate device linking operation. Embodiments of the present invention may extract device code from their respective host object files and then linked them together to form linked device code. This linked device code may then be embedded back into a host object generated by embodiments of the present invention which may then be passed to a host linker to form a host executable file. As such, device code may be split into multiple files and then linked together to form a final executable file by embodiments of the present invention.
摘要翻译：本发明的实施例提供了一种新颖的解决方案，其支持在异构编程环境中使用的主机代码和设备代码的单独编译。本发明的实施例可操作以使用单独的设备链接操作链接嵌入在多个主机对象文件内的设备代码。本发明的实施例可以从其各自的主机对象文件中提取设备代码，然后将它们链接在一起以形成链接的设备代码。然后将该链接的设备代码嵌入到由本发明的实施例生成的主机对象中，然后可以将其传递到主机链接器以形成主机可执行文件。因此，设备代码可以被分割成多个文件，然后通过本发明的实施例链接在一起以形成最终的可执行文件。

8. 发明申请

US20130117548A1 ALGORITHM FOR VECTORIZATION AND MEMORY COALESCING DURING COMPILING 有权
标题翻译：在编译过程中进行视觉和记忆分析的算法
公开(公告)号：US20130117548A1
公开(公告)日：2013-05-09
申请号：US13660986
申请日：2012-10-25
申请人： NVIDIA Corporation
发明人： Vinod Grover , Manjunath Kudlur , Michael Murphy
IPC分类号： G06F9/30
CPC分类号： G06F8/443 , G06F8/41 , G06F8/433 , G06F8/4442 , G06F8/445 , G06F8/45 , G06F8/456 , G06F9/5066
摘要： One embodiment of the present invention sets forth a technique for reducing the number of assembly instructions included in a computer program. The technique involves receiving a directed acyclic graph (DAG) that includes a plurality of nodes, where each node includes an assembly instruction of the computer program, hierarchically parsing the plurality of nodes to identify at least two assembly instructions that are vectorizable and can be replaced by a single vectorized assembly instruction, and replacing the at least two assembly instructions with the single vectorized assembly instruction.
摘要翻译：本发明的一个实施例提出了一种用于减少包括在计算机程序中的组装指令数量的技术。该技术涉及接收包括多个节点的有向非循环图（DAG），其中每个节点包括计算机程序的汇编指令，分层解析多个节点以识别可向量化并且可以被替换的至少两个汇编指令通过单个向量化的组装指令，并用单个向量化的组装指令替换该至少两个组装指令。

9. 发明公开

US20240264853A1 JUST IN TIME COMPILATION USING LINK TIME OPTIMIZATION 审中-公开
公开(公告)号：US20240264853A1
公开(公告)日：2024-08-08
申请号：US18637355
申请日：2024-04-16
申请人： NVIDIA Corporation
发明人： Michael Murphy , Shelton George Dsouza , Shandeep Nagori , Thibaut Lutz
IPC分类号： G06F9/455 , G06F9/445
CPC分类号： G06F9/4552 , G06F9/44521
摘要： A first intermediate representation of a first portion of a source code implementing an application and a second intermediate representation of a second portion of the source code is received by a processing device. The first intermediate representation and the second intermediate representation is merged, at run-time, into a merged intermediate representation, wherein the first intermediate representation includes a reference to a function in the second intermediate representation. An execution flow transfer instruction within the merged intermediate representation is identified based on a run-time value of a parameter of the application. The execution flow transfer instruction references the function. A set of executable instructions implementing the function is identified within the merged intermediate representation. The execution flow transfer instruction is replaced with a copy of the set of executable instructions implementing the function.

10. 发明授权

US11972281B2 Just in time compilation using link time optimization 有权
公开(公告)号：US11972281B2
公开(公告)日：2024-04-30
申请号：US17688797
申请日：2022-03-07
申请人： NVIDIA Corporation
发明人： Michael Murphy , Shelton George Dsouza , Shandeep Nagori , Thibaut Lutz
IPC分类号： G06F9/445 , G06F9/455
CPC分类号： G06F9/4552 , G06F9/44521
摘要： A first intermediate representation of a first portion of a source code implementing an application and a second intermediate representation of a second portion of the source code is received by a processing device. The first intermediate representation and the second intermediate representation is merged, at run-time, into a merged intermediate representation, wherein the first intermediate representation includes a reference to a function in the second intermediate representation. An execution flow transfer instruction within the merged intermediate representation is identified based on a run-time value of a parameter of the application. The execution flow transfer instruction references the function. A set of executable instructions implementing the function is identified within the merged intermediate representation. The execution flow transfer instruction is replaced with a copy of the set of executable instructions implementing the function.

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