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1. 发明授权

US09484115B1 Power savings via selection of SRAM power source 有权
标题翻译：通过选择SRAM电源节约能源
公开(公告)号：US09484115B1
公开(公告)日：2016-11-01
申请号：US14711712
申请日：2015-05-13
申请人： NVIDIA CORPORATION
发明人： Stephen Felix , Hwong-Kwo Lin , Spencer Gold , Jing Guo , Andreas Gotterba , Jason Golbus , Karthik Natarajan , Jun Yang , Zhenye Jiang , Ge Yang , Lei Wang , Yong Li , Hua Chen , Haiyan Gong , Beibei Ren , Eric Voelkel
IPC分类号： G11C29/08 , G11C11/16 , G11C7/00 , G11C5/14
CPC分类号： G11C11/1697 , G11C5/143 , G11C7/00 , G11C11/417 , G11C29/08 , G11C2207/2227
摘要： A subsystem configured to select the power supply to a static random access memory cell compares the level of a dedicated memory supply voltage to the primary system supply voltage. The subsystem then switches the primary system supply to the SRAM cell when the system voltage is higher than the memory supply voltage with some margin. When the system voltage is lower than the memory supply voltage, with margin, the subsystem switches the memory supply to the SRAM cell. When the system voltage is comparable to the memory supply, the subsystem switches the system voltage to the SRAM cell if performance is a prioritized consideration, but switches the memory supply to the SRAM cell if power reduction is a prioritized consideration. In this manner, the system achieves optimum performance without incurring steady state power losses and avoids timing issues in accessing memory.
摘要翻译：被配置为选择对静态随机存取存储器单元的电源的子系统将专用存储器电源电压的电平与主系统电源电压进行比较。当系统电压高于具有一定余量的存储器电源电压时，子系统将主系统电源切换到SRAM单元。当系统电压低于存储器电源电压时，子系统将存储器电源切换到SRAM单元。当系统电压与存储器电源相当时，如果性能是优先考虑的话，子系统将系统电压切换到SRAM单元，但如果降低功耗是优先考虑的话，将存储器电源切换到SRAM单元。以这种方式，系统实现最佳性能而不会导致稳态功率损耗，并避免访问存储器时的定时问题。

2. 发明申请

US20140084984A1 LOW POWER, SINGLE-RAIL LEVEL SHIFTERS EMPLOYING POWER DOWN SIGNAL FROM OUTPUT POWER DOMAIN AND A METHOD OF CONVERTING A DATA SIGNAL BETWEEN POWER DOMAINS 有权
标题翻译：低功率，单轨电平切换器，用于从输出电源域使用掉电信号，以及转换电源域之间的数据信号的方法
公开(公告)号：US20140084984A1
公开(公告)日：2014-03-27
申请号：US13626100
申请日：2012-09-25
申请人： NVIDIA CORPORATION
发明人： Hank Lin , Ge Yang , Xi Zhang , Jiani Yu , Haiyan Gong
IPC分类号： H03L5/00
CPC分类号： H03K19/017509 , H03K19/018507
摘要： Provided herein is a voltage level shifter, an apparatus including a voltage level shifter and a method of converting voltages between input and output power domains. In one embodiment, the voltage level shifter includes: (1) an input circuit configured to receive a data signal from an input power domain and a power down signal from a output power domain and (2) a transition circuit coupled to the input circuit and configured to receive the data signal and an inverted signal of the power down signal, wherein the input circuit and the transition circuit are both configured to connect to a supply voltage of the output power domain as a power source.
摘要翻译：本文提供了一种电压电平移位器，包括电压电平移位器的装置和在输入和输出电力域之间转换电压的方法。在一个实施例中，电压电平移位器包括：（1）被配置为从输入功率域接收数据信号的输入电路和来自输出功率域的掉电信号，以及（2）耦合到输入电路的转换电路和被配置为接收所述数据信号和所述掉电信号的反相信号，其中所述输入电路和所述转换电路都被配置为连接到所述输出功率域的电源电压作为电源。

3. 发明授权

US09842631B2 Mitigating external influences on long signal lines 有权
公开(公告)号：US09842631B2
公开(公告)日：2017-12-12
申请号：US13715991
申请日：2012-12-14
申请人： NVIDIA Corporation
发明人： Ge Yang , Hwong-Kwo Lin , Xi Zhang , Jiani Yu , Haiyan Gong
IPC分类号： G11C7/12 , G11C11/4091
CPC分类号： G11C7/12 , G11C11/4091
摘要： Mitigating external influences on long signal lines. In accordance with an embodiment of the present invention, a column of a memory array includes first and second transistors configured to pull up the bit line of the column. The column includes a third transistor configured to selectively pull up the bit line of the column responsive to a level of the inverted bit line of the column and a fourth transistor configured to selectively pull up the inverted bit line of the column responsive to a level of the bit line of the column. The column further includes fifth and sixth transistors configured to selectively pull up the bit line and inverted bit line of the column responsive to the clamp signal and a seventh transistor configured to selectively couple the bit line of the column and the inverted bit line of the column responsive to the clamp signal.

4. 发明申请

US20140169108A1 MITIGATING EXTERNAL INFLUENCES ON LONG SIGNAL LINES 有权
标题翻译：减轻对长信号线的外部影响
公开(公告)号：US20140169108A1
公开(公告)日：2014-06-19
申请号：US13715991
申请日：2012-12-14
申请人： NVIDIA CORPORATION
发明人： Ge Yang , Hwong-Kwo Lin , Xi Zhang , Jiani Yu , Haiyan Gong
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C11/4091
摘要： Mitigating external influences on long signal lines. In accordance with an embodiment of the present invention, a column of a memory array includes first and second transistors configured to pull up the bit line of the column. The column includes a third transistor configured to selectively pull up the bit line of the column responsive to a level of the inverted bit line of the column and a fourth transistor configured to selectively pull up the inverted bit line of the column responsive to a level of the bit line of the column. The column further includes fifth and sixth transistors configured to selectively pull up the bit line and inverted bit line of the column responsive to the clamp signal and a seventh transistor configured to selectively couple the bit line of the column and the inverted bit line of the column responsive to the clamp signal.
摘要翻译：减轻对长信号线的外部影响。根据本发明的实施例，存储阵列的列包括被配置为上拉列的位线的第一和第二晶体管。该列包括第三晶体管，其被配置为响应于该列的反相位线的电平有选择地上拉该列的位线;以及第四晶体管，其被配置为响应于该列的反相位线选择性地上拉该反相位线列的位线。该列还包括第五和第六晶体管，其被配置为响应钳位信号选择性地上拉该列的位线和反相位线;以及第七晶体管，被配置为选择性地耦合该列的位线和该列的反相位线响应钳位信号。

5. 发明授权

US10672461B2 Write assist negative bit line voltage generator for SRAM array 审中-公开
公开(公告)号：US10672461B2
公开(公告)日：2020-06-02
申请号：US14160706
申请日：2014-01-22
申请人： Nvidia Corporation
发明人： Haiyan Gong , Lei Wang , Sing-Rong Li , Hwong-Kwo Lin , Pai-Yi Chang
IPC分类号： G11C11/419 , G11C7/12
摘要： A negative bit line write assist system includes an array voltage supply and a static random access memory (SRAM) cell that is coupled to the array voltage supply and controlled by bit lines during a write operation. Additionally, the negative bit line write assist system includes a bit line voltage unit that is coupled to the SRAM cell, wherein a distributed capacitance is controlled by a write assist command to provide generation of a negative bit line voltage during the write operation. A negative bit line write assist method is also provided.

6. 发明授权

US09542992B2 SRAM core cell design with write assist 有权
标题翻译： SRAM核心单元设计具有写入辅助功能
公开(公告)号：US09542992B2
公开(公告)日：2017-01-10
申请号：US13865281
申请日：2013-04-18
申请人： NVIDIA CORPORATION
发明人： Hwong-Kwo Lin , Ge Yang , Fei Song , Xi Zhang , Haiyan Gong
IPC分类号： G11C11/412
CPC分类号： G11C11/412
摘要： A static random access memory (SRAM) cell includes a storage unit configured to store a data bit in a storage node. The SRAM cell further includes an access unit coupled to the storage unit. The access unit is configured to transfer current to the storage node when a word line is asserted. The SRAM cell further includes a row header configured to provide current from a power supply when the word line is not asserted, and to not provide current from the power supply when the word line is asserted. The SRAM cell further includes a column header configured to provide current from a power supply when a write column line is not asserted, and to not provide current from the power supply when the write column line is asserted.
摘要翻译：静态随机存取存储器（SRAM）单元包括被配置为在存储节点中存储数据位的存储单元。 SRAM单元还包括耦合到存储单元的存取单元。访问单元被配置为当字线被断言时将电流传送到存储节点。 SRAM单元进一步包括行标头，其被配置为当字线未被断言时提供来自电源的电流，并且当字线被断言时不提供来自电源的电流。 SRAM单元进一步包括列头，其配置成当写入列线未被置位时提供来自电源的电流，并且当写入列线被断言时不提供来自电源的电流。

7. 发明授权

US09355710B2 Hybrid approach to write assist for memory array 有权
标题翻译：对存储器阵列的写入辅助的混合方法
公开(公告)号：US09355710B2
公开(公告)日：2016-05-31
申请号：US14162639
申请日：2014-01-23
申请人： Nvidia Corporation
发明人： Haiyan Gong , Lei Wang , Sing-Rong Li , Hwong-Kwo Lin , Pai-Yi Chang
IPC分类号： G11C11/412 , G11C11/419 , G11C5/14
CPC分类号： G11C11/419 , G11C5/147
摘要： A hybrid write-assist memory system includes an array voltage supply and a static random access memory (SRAM) cell that is controlled by bit lines and a word line and employs a separable cell supply voltage coupled to the array voltage supply. Additionally, the hybrid write-assist memory system includes a supply voltage droop unit that is coupled to the SRAM cell and provides a voltage reduction of the separable cell supply voltage during a write operation. Also, the hybrid write-assist memory system includes a negative bit line unit that is coupled to the supply voltage droop unit and provides a negative bit line voltage concurrently with the voltage reduction of the separable cell supply voltage during the write operation. A method of operating a hybrid write-assist memory system is also provided.
摘要翻译：混合写入辅助存储器系统包括阵列电压源和由位线和字线控制的静态随机存取存储器（SRAM）单元，并采用耦合到阵列电压源的可分离单元电源电压。此外，混合写入辅助存储器系统包括耦合到SRAM单元的电源电压下降单元，并且在写入操作期间提供可分离单元电源电压的电压降低。此外，混合写辅助存储器系统包括负位线单元，其耦合到电源电压下降单元，并且在写操作期间与可分离单元电源电压的电压降低同时提供负位线电压。还提供了一种操作混合写入辅助存储器系统的方法。

8. 发明申请

US20150206577A1 HYBRID APPROACH TO WRITE ASSIST FOR MEMORY ARRAY 有权
标题翻译：用于存储阵列的写入协议的混合方法
公开(公告)号：US20150206577A1
公开(公告)日：2015-07-23
申请号：US14162639
申请日：2014-01-23
申请人： Nvidia Corporation
发明人： Haiyan Gong , Lei Wang , Sing-Rong Li , Hwong-Kwo Lin , Pai-Yi Chang
IPC分类号： G11C11/419 , G11C5/14
CPC分类号： G11C11/419 , G11C5/147
摘要： A hybrid write-assist memory system includes an array voltage supply and a static random access memory (SRAM) cell that is controlled by bit lines and a word line and employs a separable cell supply voltage coupled to the array voltage supply. Additionally, the hybrid write-assist memory system includes a supply voltage droop unit that is coupled to the SRAM cell and provides a voltage reduction of the separable cell supply voltage during a write operation. Also, the hybrid write-assist memory system includes a negative bit line unit that is coupled to the supply voltage droop unit and provides a negative bit line voltage concurrently with the voltage reduction of the separable cell supply voltage during the write operation. A method of operating a hybrid write-assist memory system is also provided.
摘要翻译：混合写入辅助存储器系统包括阵列电压源和由位线和字线控制的静态随机存取存储器（SRAM）单元，并采用耦合到阵列电压源的可分离单元电源电压。此外，混合写入辅助存储器系统包括耦合到SRAM单元的电源电压下降单元，并且在写入操作期间提供可分离单元电源电压的电压降低。此外，混合写辅助存储器系统包括负位线单元，其耦合到电源电压下降单元，并且在写操作期间与可分离单元电源电压的电压降低同时提供负位线电压。还提供了一种操作混合写入辅助存储器系统的方法。

9. 发明申请

US20150206576A1 NEGATIVE BIT LINE WRITE ASSIST FOR MEMORY ARRAY 审中-公开
标题翻译：用于存储阵列的负号位线写入
公开(公告)号：US20150206576A1
公开(公告)日：2015-07-23
申请号：US14160706
申请日：2014-01-22
申请人： Nvidia Corporation
发明人： Haiyan Gong , Lei Wang , Sing-Rong Li , Hwong-Kwo Lin , Pai-Yi Chang
IPC分类号： G11C11/419 , G11C5/14 , G11C7/12
CPC分类号： G11C11/419 , G11C7/12
摘要： A negative bit line write assist system includes an array voltage supply and a static random access memory (SRAM) cell that is coupled to the array voltage supply and controlled by bit lines during a write operation. Additionally, the negative bit line write assist system includes a bit line voltage unit that is coupled to the SRAM cell, wherein a distributed capacitance is controlled by a write assist command to provide generation of a negative bit line voltage during the write operation. A negative bit line write assist method is also provided.
摘要翻译：负位线写入辅助系统包括阵列电压源和静态随机存取存储器（SRAM）单元，其在写入操作期间耦合到阵列电压源并由位线控制。此外，负位线写入辅助系统包括耦合到SRAM单元的位线电压单元，其中通过写入辅助命令来控制分布电容，以在写入操作期间提供负位线电压的产生。还提供了一种负位线写入辅助方法。

10. 发明授权

US09071240B2 Low power, single-rail level shifters employing power down signal from output power domain and a method of converting a data signal between power domains 有权
标题翻译：采用输出功率域的掉电信号的低功率，单轨电平移位器以及在功率域之间转换数据信号的方法
公开(公告)号：US09071240B2
公开(公告)日：2015-06-30
申请号：US13626100
申请日：2012-09-25
申请人： Nvidia Corporation
发明人： Hank Lin , Ge Yang , Xi Zhang , Jiani Yu , Haiyan Gong
IPC分类号： H03L5/00 , H03K19/0175 , H03K19/0185
CPC分类号： H03K19/017509 , H03K19/018507
摘要： Provided herein is a voltage level shifter, an apparatus including a voltage level shifter and a method of converting voltages between input and output power domains. In one embodiment, the voltage level shifter includes: (1) an input circuit configured to receive a data signal from an input power domain and a power down signal from a output power domain and (2) a transition circuit coupled to the input circuit and configured to receive the data signal and an inverted signal of the power down signal, wherein the input circuit and the transition circuit are both configured to connect to a supply voltage of the output power domain as a power source.
摘要翻译：本文提供了一种电压电平移位器，包括电压电平移位器的装置和在输入和输出电力域之间转换电压的方法。在一个实施例中，电压电平移位器包括：（1）被配置为从输入功率域接收数据信号的输入电路和来自输出功率域的掉电信号，以及（2）耦合到输入电路的转换电路和被配置为接收所述数据信号和所述掉电信号的反相信号，其中所述输入电路和所述转换电路都被配置为连接到所述输出功率域的电源电压作为电源。

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