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1. 发明授权

US10672461B2 Write assist negative bit line voltage generator for SRAM array 审中-公开
公开(公告)号：US10672461B2
公开(公告)日：2020-06-02
申请号：US14160706
申请日：2014-01-22
申请人： Nvidia Corporation
发明人： Haiyan Gong , Lei Wang , Sing-Rong Li , Hwong-Kwo Lin , Pai-Yi Chang
IPC分类号： G11C11/419 , G11C7/12
摘要： A negative bit line write assist system includes an array voltage supply and a static random access memory (SRAM) cell that is coupled to the array voltage supply and controlled by bit lines during a write operation. Additionally, the negative bit line write assist system includes a bit line voltage unit that is coupled to the SRAM cell, wherein a distributed capacitance is controlled by a write assist command to provide generation of a negative bit line voltage during the write operation. A negative bit line write assist method is also provided.

2. 发明授权

US09355710B2 Hybrid approach to write assist for memory array 有权
标题翻译：对存储器阵列的写入辅助的混合方法
公开(公告)号：US09355710B2
公开(公告)日：2016-05-31
申请号：US14162639
申请日：2014-01-23
申请人： Nvidia Corporation
发明人： Haiyan Gong , Lei Wang , Sing-Rong Li , Hwong-Kwo Lin , Pai-Yi Chang
IPC分类号： G11C11/412 , G11C11/419 , G11C5/14
CPC分类号： G11C11/419 , G11C5/147
摘要： A hybrid write-assist memory system includes an array voltage supply and a static random access memory (SRAM) cell that is controlled by bit lines and a word line and employs a separable cell supply voltage coupled to the array voltage supply. Additionally, the hybrid write-assist memory system includes a supply voltage droop unit that is coupled to the SRAM cell and provides a voltage reduction of the separable cell supply voltage during a write operation. Also, the hybrid write-assist memory system includes a negative bit line unit that is coupled to the supply voltage droop unit and provides a negative bit line voltage concurrently with the voltage reduction of the separable cell supply voltage during the write operation. A method of operating a hybrid write-assist memory system is also provided.
摘要翻译：混合写入辅助存储器系统包括阵列电压源和由位线和字线控制的静态随机存取存储器（SRAM）单元，并采用耦合到阵列电压源的可分离单元电源电压。此外，混合写入辅助存储器系统包括耦合到SRAM单元的电源电压下降单元，并且在写入操作期间提供可分离单元电源电压的电压降低。此外，混合写辅助存储器系统包括负位线单元，其耦合到电源电压下降单元，并且在写操作期间与可分离单元电源电压的电压降低同时提供负位线电压。还提供了一种操作混合写入辅助存储器系统的方法。

3. 发明申请

US20150206577A1 HYBRID APPROACH TO WRITE ASSIST FOR MEMORY ARRAY 有权
标题翻译：用于存储阵列的写入协议的混合方法
公开(公告)号：US20150206577A1
公开(公告)日：2015-07-23
申请号：US14162639
申请日：2014-01-23
申请人： Nvidia Corporation
发明人： Haiyan Gong , Lei Wang , Sing-Rong Li , Hwong-Kwo Lin , Pai-Yi Chang
IPC分类号： G11C11/419 , G11C5/14
CPC分类号： G11C11/419 , G11C5/147
摘要： A hybrid write-assist memory system includes an array voltage supply and a static random access memory (SRAM) cell that is controlled by bit lines and a word line and employs a separable cell supply voltage coupled to the array voltage supply. Additionally, the hybrid write-assist memory system includes a supply voltage droop unit that is coupled to the SRAM cell and provides a voltage reduction of the separable cell supply voltage during a write operation. Also, the hybrid write-assist memory system includes a negative bit line unit that is coupled to the supply voltage droop unit and provides a negative bit line voltage concurrently with the voltage reduction of the separable cell supply voltage during the write operation. A method of operating a hybrid write-assist memory system is also provided.
摘要翻译：混合写入辅助存储器系统包括阵列电压源和由位线和字线控制的静态随机存取存储器（SRAM）单元，并采用耦合到阵列电压源的可分离单元电源电压。此外，混合写入辅助存储器系统包括耦合到SRAM单元的电源电压下降单元，并且在写入操作期间提供可分离单元电源电压的电压降低。此外，混合写辅助存储器系统包括负位线单元，其耦合到电源电压下降单元，并且在写操作期间与可分离单元电源电压的电压降低同时提供负位线电压。还提供了一种操作混合写入辅助存储器系统的方法。

4. 发明申请

US20150206576A1 NEGATIVE BIT LINE WRITE ASSIST FOR MEMORY ARRAY 审中-公开
标题翻译：用于存储阵列的负号位线写入
公开(公告)号：US20150206576A1
公开(公告)日：2015-07-23
申请号：US14160706
申请日：2014-01-22
申请人： Nvidia Corporation
发明人： Haiyan Gong , Lei Wang , Sing-Rong Li , Hwong-Kwo Lin , Pai-Yi Chang
IPC分类号： G11C11/419 , G11C5/14 , G11C7/12
CPC分类号： G11C11/419 , G11C7/12
摘要： A negative bit line write assist system includes an array voltage supply and a static random access memory (SRAM) cell that is coupled to the array voltage supply and controlled by bit lines during a write operation. Additionally, the negative bit line write assist system includes a bit line voltage unit that is coupled to the SRAM cell, wherein a distributed capacitance is controlled by a write assist command to provide generation of a negative bit line voltage during the write operation. A negative bit line write assist method is also provided.
摘要翻译：负位线写入辅助系统包括阵列电压源和静态随机存取存储器（SRAM）单元，其在写入操作期间耦合到阵列电压源并由位线控制。此外，负位线写入辅助系统包括耦合到SRAM单元的位线电压单元，其中通过写入辅助命令来控制分布电容，以在写入操作期间提供负位线电压的产生。还提供了一种负位线写入辅助方法。

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