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    • 3. 发明授权
    • Address decoding method and semiconductor memory device using the same
    • 地址解码方法及使用其的半导体存储器件
    • US08588013B2
    • 2013-11-19
    • US13336840
    • 2011-12-23
    • Shin Ho Chu
    • Shin Ho Chu
    • G11C7/00
    • G11C8/18G11C29/1201G11C29/12015G11C29/18
    • A semiconductor memory device includes: a strobe clock generator configured to generate a strobe clock signal having a delay time controlled according to a plurality of test mode signals which are selectively enabled in response to a read signal or write signal; an internal address generator configured to latch an address in response to a first level of the strobe clock signal, and generate an internal address by decoding the address in response to a second level of the strobe clock signal; and an output enable signal generator configured to decode the internal address and generate output enable signals which are selectively enabled.
    • 半导体存储器件包括:选通时钟发生器,被配置为产生具有根据多个测试模式信号控制的延迟时间的选通时钟信号,所述测试模式信号响应于读取信号或写入信号被选择性地使能; 内部地址发生器,被配置为响应于所述选通时钟信号的第一电平来锁存地址,并且响应于所述选通时钟信号的第二电平对所述地址进行解码来产生内部地址; 以及输出使能信号发生器,被配置为对内部地址进行解码并产生有选择地使能的输出使能信号。
    • 5. 发明申请
    • SEMICONDUCTOR INTEGRATED CIRCUIT AND MULTI TEST METHOD THEREOF
    • 半导体集成电路及其多种测试方法
    • US20090059691A1
    • 2009-03-05
    • US12169594
    • 2008-07-08
    • Shin Ho ChuJong Won Lee
    • Shin Ho ChuJong Won Lee
    • G11C7/00G11C8/00
    • G11C29/18G11C2029/1202G11C2029/1204G11C2029/2602
    • A semiconductor integrated circuit includes a multi-mode control signal generating section that enables one of up and down mat input/output switch control signals for controlling input/output switches in up and down mats according to up/down information addresses during a read operation mode, a multi-mode decoding section that simultaneously activates multi mat selection signals corresponding to one of the up mats and one of the down mats according to row addresses in an active operation mode, and a mat control section that receives the up and down mat input/output switch control signals and the multi mat selection signals and enables word lines and input/output switches in the mats corresponding to the signals.
    • 半导体集成电路包括多模式控制信号产生部分,其能够在读操作模式期间根据上/下信息地址使得上和下输入/输出开关控制信号之一用于根据上/下信息地址来控制上/下按钮中的输入/输出开关 ,多模式解码部分,其根据活动操作模式中的行地址同时激活对应于上层和下层之一的多层选择信号;以及垫控制部分,其接收上和下垫输入 /输出开关控制信号和多功能席选择信号,并使得字符线和输入/输出开关在与信号相对应的垫中。
    • 7. 发明授权
    • Anti-fuse repair control circuit for preventing stress on circuit parts
    • 防熔丝修复控制电路,用于防止电路部件的应力
    • US07902902B2
    • 2011-03-08
    • US11964294
    • 2007-12-26
    • Shin Ho ChuMin Jung Koh
    • Shin Ho ChuMin Jung Koh
    • H01H85/00
    • G11C17/18
    • The present invention relates to an anti-fuse repair control circuit which regulates transmission of a power voltage and a back-bias voltage that are converted to repair an anti-fuse to a circuit part. As such, the present invention prevents the influence of a high power voltage or a low back-bias voltage on a circuit part such as a cell, a peripheral circuit, or a core region during an anti-fuse repair. The anti-fuse repair control circuit includes an anti-fuse repair enabling part providing an anti-fuse repair enabling signal corresponding to a repair of an anti-fuse; a power voltage control part controlling transmission of a power voltage to a first circuit part according to an enablement state of the anti-fuse repair enabling signal; and a back-bias voltage control part controlling transmission of a back-bias voltage to a second circuit part according to the enablement state of the anti-fuse repair enabling signal.
    • 本发明涉及一种反熔丝修复控制电路,其调节电源电压和反向偏置电压的传输,所述反向偏置电压被转换为修复反熔丝到电路部分。 因此,本发明在抗熔丝修复期间防止高功率电压或低背偏压对诸如电池,外围电路或芯区域的电路部分的影响。 反熔丝修复控制电路包括反熔丝修复使能部件,其提供对应于抗熔丝修复的抗熔丝修复使能信号; 电源电压控制部,根据所述反熔丝修复使能信号的使能状态,控制向第一电路部的电力电压的传输; 以及反偏压控制部,其根据反熔丝修复使能信号的使能状态来控制向第二电路部的透射。
    • 8. 发明授权
    • Internal voltage generation circuit
    • 内部电压产生电路
    • US07800431B2
    • 2010-09-21
    • US11821600
    • 2007-06-25
    • Shin Ho Chu
    • Shin Ho Chu
    • G11C5/14
    • G11C5/14G05F1/465G11C5/144
    • Various examples of internal voltage generation circuit are provided. In one example, the internal voltage generation circuit includes a level control signal generator for generating a level control signal in response to a power down mode signal, which is activated synchronously with a clock enable signal, and a precharge flag signal, which is enabled when a precharge operation, is performed, and an internal voltage generator for generating an internal voltage in response to the level control signal and outputting it to an output node.
    • 提供内部电压产生电路的各种示例。 在一个示例中,内部电压产生电路包括电平控制信号发生器,用于响应于与时钟使能信号同步激活的掉电模式信号和预充电标志信号产生电平控制信号,该预充电标志信号在 执行预充电操作,以及内部电压发生器,用于响应于电平控制信号产生内部电压并将其输出到输出节点。
    • 10. 发明申请
    • ANTI-FUSE REPAIR CONTROL CIRCUIT FOR PREVENTING STRESS ON CIRCUIT PARTS
    • 用于防止电路部件应力的防熔丝维修控制电路
    • US20090134935A1
    • 2009-05-28
    • US11964294
    • 2007-12-26
    • Shin Ho ChuMin Jung Koh
    • Shin Ho ChuMin Jung Koh
    • H01H85/00
    • G11C17/18
    • The present invention relates to an anti-fuse repair control circuit which regulates transmission of a power voltage and a back-bias voltage that are converted to repair an anti-fuse to a circuit part. As such, the present invention prevents the influence of a high power voltage or a low back-bias voltage on a circuit part such as a cell, a peripheral circuit, or a core region during an anti-fuse repair. The anti-fuse repair control circuit includes an anti-fuse repair enabling part providing an anti-fuse repair enabling signal corresponding to a repair of an anti-fuse; a power voltage control part controlling transmission of a power voltage to a first circuit part according to an enablement state of the anti-fuse repair enabling signal; and a back-bias voltage control part controlling transmission of a back-bias voltage to a second circuit part according to the enablement state of the anti-fuse repair enabling signal.
    • 本发明涉及一种反熔丝修复控制电路,其调节电源电压和反向偏置电压的传输,所述反向偏置电压被转换为修复反熔丝到电路部分。 因此,本发明在抗熔丝修复期间防止高功率电压或低背偏压对诸如电池,外围电路或芯区域的电路部分的影响。 反熔丝修复控制电路包括反熔丝修复使能部件,其提供对应于抗熔丝修复的抗熔丝修复使能信号; 电源电压控制部,根据所述反熔丝修复使能信号的使能状态,控制向第一电路部的电力电压的传输; 以及反偏压控制部,其根据反熔丝修复使能信号的使能状态来控制向第二电路部的透射。