专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07872932B2 Method of precharging local input/output line and semiconductor memory device using the method 失效
标题翻译：使用该方法对本地输入/输出线和半导体存储器件进行预充电的方法
公开(公告)号：US07872932B2
公开(公告)日：2011-01-18
申请号：US12187269
申请日：2008-08-06
申请人： Myeong-O Kim , Byung-Chul Kim , Yong-Gyu Chu
发明人： Myeong-O Kim , Byung-Chul Kim , Yong-Gyu Chu
IPC分类号： G11C7/00
CPC分类号： G11C7/1048 , G11C7/12 , G11C8/18
摘要： A method and semiconductor memory device for precharging a local input/output line. The semiconductor memory device, which may have an open bit line structure, transmits data through local input/output lines that are coupled to bit lines of first to n-th memory cell array blocks (n being a natural number). The semiconductor memory device may include a precharge unit configured to generate a plurality of precharge signals and a controller configured to control precharging of the at least one local input/output line responsive to block information corresponding to activation of at least one of the memory cell array blocks and responsive to at least one of the precharge signals.
摘要翻译：一种用于对本地输入/输出线进行预充电的方法和半导体存储器件。可以具有开放位线结构的半导体存储器件通过耦合到第一至第n存储器单元阵列块（n为自然数）的位线的本地输入/输出线传输数据。半导体存储器件可以包括：预充电单元，其被配置为产生多个预充电信号;以及控制器，被配置为响应于对应于至少一个存储单元阵列的激活来控制至少一个本地输入/输出线的预充电并且响应于至少一个预充电信号。

2. 发明授权

US08315118B2 Precharge method of semiconductor memory device and semiconductor memory device using the same 有权
标题翻译：半导体存储器件的预充电方法及使用其的半导体存储器件
公开(公告)号：US08315118B2
公开(公告)日：2012-11-20
申请号：US12767830
申请日：2010-04-27
申请人： Yong-Gyu Chu , Woo-Pyo Jeong
发明人： Yong-Gyu Chu , Woo-Pyo Jeong
IPC分类号： G11C7/00
CPC分类号： G11C8/12 , G11C7/12 , G11C11/4094
摘要： A precharge method of a semiconductor memory device that controls a precharge start time of each bank during a bank precharge operation, and a semiconductor memory device using the method, are provided. The device may latch an active or write order of respective banks and differently control precharge start times of the respective banks according to the latched active or write order during a plural-bank precharge operation to allow a plurality of banks to start precharge operations at different times.
摘要翻译：提供了一种半导体存储器件的预充电方法，其在银行预充电操作期间控制每个存储体的预充电开始时间，以及使用该方法的半导体存储器件。该装置可以锁存相应组的有效或写入顺序，并且在多组预充电操作期间根据锁存的有效或写入顺序不同地控制各个存储体的预充电开始时间，以允许多个存储体在不同时间开始预充电操作。

3. 发明授权

US07420871B2 Synchronous semiconductor memory device 失效
标题翻译：同步半导体存储器件
公开(公告)号：US07420871B2
公开(公告)日：2008-09-02
申请号：US11609865
申请日：2006-12-12
申请人： Yong-Gyu Chu
发明人： Yong-Gyu Chu
IPC分类号： G11C8/00
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/1066 , G11C7/222
摘要： Provided is a synchronous semiconductor memory device with improved latency control. In one embodiment, the synchronous semiconductor memory device may include a clock synchronizing circuit, a latency circuit, and a latency control circuit. The clock synchronizing circuit may receive an external clock signal and output a data output clock signal. The latency circuit may store a read signal in response to at least one sampling clock signal, generate a plurality of clock control signals in a sequential manner, generate a plurality of transfer clock signals synchronized with the plurality of clock control signals, and supply a latency signal in response to the transfer clock signals. The latency control circuit may delay the plurality of clock control signals by the sum of output delay time and the read command delay time so as to generate a plurality of sampling clock signals synchronized with the plurality of delayed clock control signals.
摘要翻译：提供了具有改进的等待时间控制的同步半导体存储器件。在一个实施例中，同步半导体存储器件可以包括时钟同步电路，等待时间电路和等待时间控制电路。时钟同步电路可以接收外部时钟信号并输出数据输出时钟信号。延迟电路可以响应于至少一个采样时钟信号存储读取信号，以顺序方式产生多个时钟控制信号，产生与多个时钟控制信号同步的多个传输时钟信号，并提供等待时间响应于传输时钟信号的信号。等待时间控制电路可以通过输出延迟时间和读命令延迟时间的和来延迟多个时钟控制信号，以便产生与多个延迟的时钟控制信号同步的多个采样时钟信号。

4. 发明授权

US07433252B2 Semiconductor memory device capable of storing data of various patterns and method of electrically testing the semiconductor memory device 失效
标题翻译：能够存储各种图案的数据的半导体存储器件以及对半导体存储器件进行电测试的方法
公开(公告)号：US07433252B2
公开(公告)日：2008-10-07
申请号：US11267203
申请日：2005-11-04
申请人： Gyu-Yeol Kim , Sang-Man Byun , Yong-Gyu Chu , Seok-Ho Park
发明人： Gyu-Yeol Kim , Sang-Man Byun , Yong-Gyu Chu , Seok-Ho Park
IPC分类号： G11C29/00
CPC分类号： G11C29/48 , G11C29/10 , G11C29/1201
摘要： A semiconductor memory device to which information of different data bits can be written, and a method of electrically testing the semiconductor memory device are provided. In a mode for testing a memory cell array of the semiconductor memory device, the semiconductor memory comprises a control signal generation pad capable of writing non-identical data to data input/output pads of each group when data is written to the memory cell array.
摘要翻译：提供可以写入不同数据位的信息的半导体存储器件，以及电半导体存储器件的电测试方法。在用于测试半导体存储器件的存储单元阵列的模式中，半导体存储器包括一个控制信号生成焊盘，当数据被写入存储单元阵列时，该控制信号产生焊盘能够将不相同的数据写入每个组的数据输入/输出焊盘。

5. 发明申请

US20070147167A1 SYNCHRONOUS SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：同步半导体存储器件
公开(公告)号：US20070147167A1
公开(公告)日：2007-06-28
申请号：US11609865
申请日：2006-12-12
申请人： Yong-Gyu Chu
发明人： Yong-Gyu Chu
IPC分类号： G11C8/00
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/1066 , G11C7/222
摘要： Provided is a synchronous semiconductor memory device with improved latency control. In one embodiment, the synchronous semiconductor memory device may include a clock synchronizing circuit, a latency circuit, and a latency control circuit. The clock synchronizing circuit may receive an external clock signal and output a data output clock signal. The latency circuit may store a read signal in response to at least one sampling clock signal, generate a plurality of clock control signals in a sequential manner, generate a plurality of transfer clock signals synchronized with the plurality of clock control signals, and supply a latency signal in response to the transfer clock signals. The latency control circuit may delay the plurality of clock control signals by the sum of output delay time and the read command delay time so as to generate a plurality of sampling clock signals synchronized with the plurality of delayed clock control signals.
摘要翻译：提供了具有改进的等待时间控制的同步半导体存储器件。在一个实施例中，同步半导体存储器件可以包括时钟同步电路，等待时间电路和等待时间控制电路。时钟同步电路可以接收外部时钟信号并输出数据输出时钟信号。延迟电路可以响应于至少一个采样时钟信号存储读取信号，以顺序方式产生多个时钟控制信号，产生与多个时钟控制信号同步的多个传输时钟信号，并提供等待时间响应于传输时钟信号的信号。等待时间控制电路可以通过输出延迟时间和读命令延迟时间的和来延迟多个时钟控制信号，以便产生与多个延迟的时钟控制信号同步的多个采样时钟信号。

6. 发明申请

US20060098506A1 Semiconductor memory device capable of storing data of various patterns and method of electrically testing the semiconductor memory device 失效
标题翻译：能够存储各种图案的数据的半导体存储器件以及对半导体存储器件进行电测试的方法
公开(公告)号：US20060098506A1
公开(公告)日：2006-05-11
申请号：US11267203
申请日：2005-11-04
申请人： Gyu-Yeol Kim , Sang-Man Byun , Yong-Gyu Chu , Seok-Ho Park
发明人： Gyu-Yeol Kim , Sang-Man Byun , Yong-Gyu Chu , Seok-Ho Park
IPC分类号： G11C29/00
CPC分类号： G11C29/48 , G11C29/10 , G11C29/1201
摘要： A semiconductor memory device to which information of different data bits can be written, and a method of electrically testing the semiconductor memory device are provided. In a mode for testing a memory cell array of the semiconductor memory device, the semiconductor memory comprises a control signal generation pad capable of writing non-identical data to data input/output pads of each group when data is written to the memory cell array.
摘要翻译：提供可以写入不同数据位的信息的半导体存储器件，以及电半导体存储器件的电测试方法。在用于测试半导体存储器件的存储单元阵列的模式中，半导体存储器包括一个控制信号生成焊盘，当数据被写入存储单元阵列时，该控制信号产生焊盘能够将不相同的数据写入每个组的数据输入/输出焊盘。

7. 发明授权

US06678206B2 Semiconductor memory device including standby mode for reducing current consumption of delay locked loop 有权
标题翻译：半导体存储器件包括用于减少延迟锁定环路的电流消耗的待机模式
公开(公告)号：US06678206B2
公开(公告)日：2004-01-13
申请号：US10106931
申请日：2002-03-25
申请人： Yong-Gyu Chu , Kyu-Chan Lee
发明人： Yong-Gyu Chu , Kyu-Chan Lee
IPC分类号： G11C800
CPC分类号： G11C8/18 , G11C7/22 , G11C7/222 , G11C2207/2227 , H03L7/0812 , H03L7/089 , H03L7/0891
摘要： A semiconductor memory device including a delay locked loop (DLL) that is capable of turning off the DLL in a precharge mode while maintaining locking information stored before the DLL operates in the precharge mode is provided. The DLL includes an ON/OFF mode for turning the DLL on or off. The DLL also includes a standby mode for turning the DLL off while still maintaining locking information stored before the DLL operates in a precharge mode in response to the activation of a standby enabling signal. The standby enabling signal is inactive when the DLL locks. The standby enabling signal is active when DLL lock is complete.
摘要翻译：提供一种包括延迟锁定环（DLL）的半导体存储器件，其能够在保持DLL在预充电模式之前存储的锁定信息的同时以预充电模式关闭DLL。该DLL包括用于打开或关闭DLL的ON / OFF模式。 DLL还包括用于响应于待机使能信号的激活而在DLL在预充电模式之前存储的锁定信息的同时仍然保持关闭DLL的待机模式。当DLL锁定时，待机启用信号无效。当DLL锁定完成时，待机启用信号有效。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式