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    • 7. 发明授权
    • Semiconductor device with conductive plugs
    • 带导电插头的半导体器件
    • US6004839A
    • 1999-12-21
    • US804112
    • 1997-02-20
    • Yoshihiro HayashiNobuhiro TanabeTsuneo TakeuchiShinobu Saito
    • Yoshihiro HayashiNobuhiro TanabeTsuneo TakeuchiShinobu Saito
    • H01L21/768H01L21/8242H01L21/8246H01L21/8238
    • H01L27/11502H01L21/768H01L27/10844H01L27/10852H01L27/11507
    • In a method of manufacturing a semiconductor device, a CMOS section composed of an N-channel MOS transistor and a P-channel MOS transistor and a memory section composed of at least a transfer gate MOS transistor is formed on a substrate. A plurality of conductive plugs is formed to penetrate a laminate insulating film to the MOS transistors. The laminate insulating film is composed of a first insulating film and a second insulating film. A capacitor section is formed on the laminate insulating film and the capacitor section is composed of an upper electrode, a dielectric film and a lower electrode. A third insulating film is formed on the laminate insulating film and the capacitor section. A wiring pattern is formed on the third insulating film to partially penetrate the second insulating film connect to the plurality of conductive plugs. A wiring pattern may be disposed in the laminate insulating film to connect at least two of the plurality of conductive plugs.
    • 在制造半导体器件的方法中,在衬底上形成由N沟道MOS晶体管和P沟道MOS晶体管组成的CMOS部分和至少由传输门MOS晶体管组成的存储部分。 形成多个导电插塞以穿透层压绝缘膜到MOS晶体管。 层叠绝缘膜由第一绝缘膜和第二绝缘膜构成。 在层叠绝缘膜上形成电容器部,电容部由上部电极,电介质膜和下部电极构成。 在层压绝缘膜和电容器部分上形成第三绝缘膜。 在第三绝缘膜上形成布线图案,以部分地穿透连接到多个导电插塞的第二绝缘膜。 布线图案可以布置在层压绝缘膜中以连接多个导电插塞中的至少两个。