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1. 发明申请

US20060209519A1 Devices having compliant wafer-level input/output interconnections and packages using pillars and methods of fabrication thereof 有权
公开(公告)号：US20060209519A1
公开(公告)日：2006-09-21
申请号：US11416686
申请日：2006-05-03
申请人： Muhannad Bakir , Kevin Martin , James Meindl
发明人： Muhannad Bakir , Kevin Martin , James Meindl
IPC分类号： H01R9/00
CPC分类号： G01R31/2863 , G01R1/0491 , G02B6/12002 , G02B6/42 , G02B6/43 , G02B2006/12107 , H01L23/49811 , H01L2224/81141 , H01L2224/81193 , H05K3/303 , H05K3/326 , H05K2203/167 , Y02P70/613
摘要： Devices having one or more of the following: an input/output (I/O) interconnect system, an optical I/O interconnect, an electrical I/O interconnect, a radio frequency I/O interconnect, are disclosed. A representative I/O interconnect system includes a first substrate and a second substrate. The first substrate includes a compliant pillar vertically extending from the first substrate. The compliant pillar is constructed a first material. The second substrate includes a compliant socket adapted to receive the compliant pillar. The compliant socket is constructed of a second material.

2. 发明申请

US20050257709A1 Systems and methods for three-dimensional lithography and nano-indentation 审中-公开
标题翻译：三维光刻和纳米压痕的系统和方法
公开(公告)号：US20050257709A1
公开(公告)日：2005-11-24
申请号：US10699287
申请日：2003-10-31
申请人： Tony Mule , Paul Kohl , Muhannad Bakir , Kevin Martin , James Meindl , Hiren Thacker
发明人： Tony Mule , Paul Kohl , Muhannad Bakir , Kevin Martin , James Meindl , Hiren Thacker
IPC分类号： B41F1/00 , B81C1/00 , G03F7/00
CPC分类号： G03F7/00 , B81B2201/042 , B81B2201/047 , B81B2201/058 , B81B2203/0384 , B81C1/00119 , B81C2201/0108 , B81C2201/0152 , B81C2201/0159 , B82Y10/00 , B82Y40/00 , G03F7/0002 , G03F7/0015
摘要： Systems and methods for three dimensional lithography, nano-indentation, and combinations thereof are disclosed. One exemplary three dimensional lithography method, among others, includes: providing a substrate having at least one optical element, wherein the optical element is selected from a refractive element and a diffractive element; disposing a polymer layer on the substrate and the at least one optical element, wherein the polymer layer includes a polymer material selected from a positive-tone polymer material and a negative-tone polymer material; positioning a mask adjacent the polymer layer, wherein the mask does not cover at least one directly exposed portion of the polymer material directly overlaying the at least one element; and exposing the at least one directly exposed portion of the polymer material to optical energy, wherein the optical energy passes through the at least one directly exposed portion of the polymer material and interacts with the element, and the element redirects the optical energy through the polymer material forming at least one area of indirectly exposed polymer material.
摘要翻译：公开了用于三维光刻，纳米压痕及其组合的系统和方法。一种示例性的三维光刻方法，其中包括：提供具有至少一个光学元件的衬底，其中所述光学元件选自折射元件和衍射元件; 在所述基板和所述至少一个光学元件上设置聚合物层，其中所述聚合物层包括选自正性聚合物材料和负性聚合物材料的聚合物材料; 将掩模定位在所述聚合物层附近，其中所述掩模不覆盖直接覆盖所述至少一个元件的聚合物材料的至少一个直接暴露部分; 并且将所述聚合物材料的至少一个直接暴露部分暴露于光能，其中所述光能通过所述聚合物材料的所述至少一个直接暴露部分并且与所述元件相互作用，并且所述元件将所述光能重定向通过所述聚合物形成间接暴露的聚合物材料的至少一个区域的材料。

3. 发明申请

US20060104566A1 Microfluidic, optical, and electrical input output interconnects, methods of fabrication thereof, and methods of use thereof 有权
标题翻译：微流体，光学和电输入输出互连，其制造方法及其使用方法
公开(公告)号：US20060104566A1
公开(公告)日：2006-05-18
申请号：US11261149
申请日：2005-10-28
申请人： Muhannad Bakir , James Meindl
发明人： Muhannad Bakir , James Meindl
IPC分类号： G02B6/12
CPC分类号： B81B7/0006 , B01J2219/0081 , B01L3/502715 , B01L2200/027 , B81B2201/058 , B81B2207/07 , G02B6/24
摘要： Input/output (I/O) interconnects, fluidic I/O interconnects, electrical, optical, and fluidic I/O interconnects, devices incorporating the I/O interconnects, systems incorporating the I/O interconnects, and methods of fabricating the I/O interconnects, devices, and systems, are described herein.
摘要翻译：输入/输出（I / O）互连，流体I / O互连，电气，光学和流体I / O互连，并入I / O互连的设备，并入I / O互连的系统，以及制造I / O互连，设备和系统。

4. 发明申请

US20110291643A1 MODULAR NANO AND MICROSCALE SENSORS 有权
标题翻译：模块化纳米和微结构传感器
公开(公告)号：US20110291643A1
公开(公告)日：2011-12-01
申请号：US13151148
申请日：2011-06-01
申请人： RAMASAMY RAVINDRAN , Muhannad Bakir
发明人： RAMASAMY RAVINDRAN , Muhannad Bakir
IPC分类号： G01R1/20
CPC分类号： G01N27/3278
摘要： Exemplary embodiments of the present invention disclose a modular testing assay. According to various embodiments of the present invention, the sensor arrays, or microplates, are removably attached to a substrate. In some embodiments, the electrical connection between the sensors of the sensor array and the substrate provide for the removal of one sensor array or microplate with another or similar sensor array. The sensor arrays can be aligned using various types of alignment devices or the substrate can be configured to allow various alignments and spatial orientations of one or more sensor arrays.
摘要翻译：本发明的示例性实施方案公开了模块化测试测定。根据本发明的各种实施例，传感器阵列或微孔板可移除地附接到基底。在一些实施例中，传感器阵列的传感器和衬底之间的电连接提供了一个传感器阵列或微板与另一个或类似的传感器阵列的去除。可以使用各种类型的对准装置来对准传感器阵列，或者可以将衬底配置成允许一个或多个传感器阵列的各种对准和空间取向。

5. 发明授权

US07798817B2 Integrated circuit interconnects with coaxial conductors 有权
标题翻译：集成电路与同轴导体互连
公开(公告)号：US07798817B2
公开(公告)日：2010-09-21
申请号：US11557073
申请日：2006-11-06
申请人： Paul A. Kohl , Ate He , Mark Cupta , Muhannad Bakir , Todd Spencer
发明人： Paul A. Kohl , Ate He , Mark Cupta , Muhannad Bakir , Todd Spencer
IPC分类号： H01R12/00
CPC分类号： H01L23/66 , H01L21/7682 , H01L23/5225 , H01L2223/6627 , H01L2224/16225 , H01L2924/1903 , H01L2924/3011 , H01P1/047 , H05K1/0219 , H05K3/4644 , H05K2201/09809
摘要： High performance interconnect devices, structures, and fabrication methods are provided herein. According to some embodiments of the present invention, an interconnect device used to connect components or route signals in an integrated circuit can comprise multiple conductors. A first conductor of the interconnect device can define a first conductor axis, and a second conductor of the interconnect device can define a second conductor axis. The second conductor can be proximate the first conduct such that first conductor axis is substantially coaxially situated relative to the second conductor axis to provide a high performance interconnect having a coaxial alignment. The first conductor and the second conductor can define a gap disposed between and separating the conductors. Other embodiments are also claimed and described.
摘要翻译：本文提供了高性能互连器件，结构和制造方法。根据本发明的一些实施例，用于连接集成电路中的部件或路由信号的互连装置可以包括多个导体。互连装置的第一导体可以限定第一导体轴线，并且互连装置的第二导体可以限定第二导体轴线。第二导体可以靠近第一导体，使得第一导体轴线相对于第二导体轴线基本上同轴地定位，以提供具有同轴对准的高性能互连。第一导体和第二导体可以限定设置在导体和分离导体之间的间隙。还要求保护和描述其它实施例。

6. 发明授权

US07554347B2 High input/output density optoelectronic probe card for wafer-level test of electrical and optical interconnect components, methods of fabrication, and methods of use 失效
标题翻译：用于电气和光学互连部件晶圆级测试的高输入/输出密度光电探针卡，制造方法和使用方法
公开(公告)号：US07554347B2
公开(公告)日：2009-06-30
申请号：US10390873
申请日：2003-03-17
申请人： Tony Mule′ , Hiren Thacker , Muhannad Bakir , James D. Meindl , Thomas K. Gaylord , Kevin P. Martin , Paul Kohl
发明人： Tony Mule′ , Hiren Thacker , Muhannad Bakir , James D. Meindl , Thomas K. Gaylord , Kevin P. Martin , Paul Kohl
IPC分类号： G01R31/02
CPC分类号： G02B6/138 , G01R3/00 , G01R31/311 , G02B6/12004 , G02B6/132 , G02B6/136
摘要： Optoelectronic probe cards, methods of fabrication, and methods of use, are disclosed. Briefly described, one exemplary embodiment includes an optoelectronic probe card adapted to test an electrical quality and an optical quality of an optoelectronic structure under test having electrical and optical components.
摘要翻译：公开了光电探针卡，制造方法和使用方法。简要描述，一个示例性实施例包括适于测试具有电和光学部件的被测光电结构的电气质量和光学质量的光电探针卡。

7. 发明授权

US08803509B2 Modular nano and microscale sensors 有权
标题翻译：模块化纳米和微米级传感器
公开(公告)号：US08803509B2
公开(公告)日：2014-08-12
申请号：US13151148
申请日：2011-06-01
申请人： Ramasamy Ravindran , Muhannad Bakir
发明人： Ramasamy Ravindran , Muhannad Bakir
IPC分类号： G01R1/20 , G01N27/327
CPC分类号： G01N27/3278
摘要： Exemplary embodiments of the present invention disclose a modular testing assay. According to various embodiments of the present invention, the sensor arrays, or microplates, are removably attached to a substrate. In some embodiments, the electrical connection between the sensors of the sensor array and the substrate provide for the removal of one sensor array or microplate with another or similar sensor array. The sensor arrays can be aligned using various types of alignment devices or the substrate can be configured to allow various alignments and spatial orientations of one or more sensor arrays.
摘要翻译：本发明的示例性实施方案公开了模块化测试测定。根据本发明的各种实施例，传感器阵列或微孔板可移除地附接到基底。在一些实施例中，传感器阵列的传感器和衬底之间的电连接提供了一个传感器阵列或微板与另一个或类似的传感器阵列的去除。可以使用各种类型的对准装置来对准传感器阵列，或者可以将衬底配置成允许一个或多个传感器阵列的各种对准和空间取向。

8. 发明授权

US06785458B2 Guided-wave optical interconnections embedded within a microelectronic wafer-level batch package 失效
标题翻译：引导波光学互连嵌入在微电子晶圆级批量封装内
公开(公告)号：US06785458B2
公开(公告)日：2004-08-31
申请号：US10074420
申请日：2002-02-11
申请人： Tony Mule′ , Chirag Patel , James D. Meindl , Thomas K. Gaylord , Elias N. Glytsis , Kevin P. Martin , Stephen M. Schultz , Muhannad Bakir , Hollie Reed , Paul Kohl
发明人： Tony Mule′ , Chirag Patel , James D. Meindl , Thomas K. Gaylord , Elias N. Glytsis , Kevin P. Martin , Stephen M. Schultz , Muhannad Bakir , Hollie Reed , Paul Kohl
IPC分类号： G02B610
CPC分类号： G02B6/43 , G02B6/10 , G02B6/12002 , G02B6/1221 , G02B6/132 , G02B6/136 , G02B6/34 , G02B2006/12107
摘要： Wafer-level electronic packages having waveguides and methods of fabricating chip-level electronic packages having waveguides are disclosed. A representative chip-level electronic package includes at least one waveguide having a waveguide core. In addition, another representative chip-level electronic package includes a waveguide having an air-gap cladding layer around a portion of the waveguide core. A representative method for fabricating a chip-level electronic package includes: providing a substrate having a passivation layer disposed on the substrate; disposing a waveguide core on a portion of the passivation layer; disposing a first sacrificial layer onto at least one portion of the passivation layer and the waveguide core; disposing an overcoat layer onto the passivation layer and the first sacrificial layer; and removing the first sacrificial layer to define an air-gap cladding layer within the overcoat polymer layer and around a portion of the waveguide core.
摘要翻译：公开了具有波导的晶片级电子封装以及制造具有波导的芯片级电子封装的方法。代表性的芯片级电子封装包括至少一个具有波导芯的波导。此外，另一代表性的芯片级电子封装包括在波导芯的一部分周围具有气隙包覆层的波导。用于制造芯片级电子封装的代表性方法包括：提供具有设置在基板上的钝化层的基板; 在所述钝化层的一部分上设置波导芯; 在所述钝化层和所述波导芯的至少一部分上设置第一牺牲层; 在所述钝化层和所述第一牺牲层上设置外涂层; 以及去除所述第一牺牲层以在所述外涂层聚合物层内和所述波导芯的一部分周围限定气隙包覆层。

9. 发明授权

US06954576B2 Guided-wave optical interconnections embedded within a microelectronic wafer-level batch package 失效
标题翻译：引导波光学互连嵌入在微电子晶圆级批量封装内
公开(公告)号：US06954576B2
公开(公告)日：2005-10-11
申请号：US10895685
申请日：2004-07-21
申请人： Tony Mule′ , Chirag Patel , James D. Meindl , Thomas K. Gaylord , Elias N. Glytsis , Kevin P. Martin , Stephen M. Schultz , Muhannad Bakir , Hollie Reed , Paul Kohl
发明人： Tony Mule′ , Chirag Patel , James D. Meindl , Thomas K. Gaylord , Elias N. Glytsis , Kevin P. Martin , Stephen M. Schultz , Muhannad Bakir , Hollie Reed , Paul Kohl
IPC分类号： G02B6/10 , G02B6/12 , G02B6/122 , G02B6/132 , G02B6/136 , G02B6/34 , G02B6/43
CPC分类号： G02B6/43 , G02B6/10 , G02B6/12002 , G02B6/1221 , G02B6/132 , G02B6/136 , G02B6/34 , G02B2006/12107
摘要： Wafer-level electronic packages having waveguides and methods of fabricating chip-level electronic packages having waveguides are disclosed. A representative chip-level electronic package includes at least one waveguide having a waveguide core. In addition, another representative chip-level electronic package includes a waveguide having an air-gap cladding layer around a portion of the waveguide core. A representative method for fabricating a chip-level electronic package includes: providing a substrate having a passivation layer disposed on the substrate; disposing a waveguide core on a portion of the passivation layer; disposing a first sacrificial layer onto at least one portion of the passivation layer and the waveguide core; disposing an overcoat layer onto the passivation layer and the first sacrificial layer; and removing the first sacrificial layer to define an air-gap cladding layer within the overcoat polymer layer and around a portion of the waveguide core.
摘要翻译：公开了具有波导的晶片级电子封装以及制造具有波导的芯片级电子封装的方法。代表性的芯片级电子封装包括至少一个具有波导芯的波导。此外，另一代表性的芯片级电子封装包括在波导芯的一部分周围具有气隙包覆层的波导。用于制造芯片级电子封装的代表性方法包括：提供具有设置在基板上的钝化层的基板; 在所述钝化层的一部分上设置波导芯; 在所述钝化层和所述波导芯的至少一部分上设置第一牺牲层; 在所述钝化层和所述第一牺牲层上设置外涂层; 以及去除所述第一牺牲层以在所述外涂层聚合物层内和所述波导芯的一部分周围限定气隙包覆层。

10. 发明授权

US06788867B2 Backplane, printed wiring board, and/or multi-chip module-level optical interconnect layer having embedded air-gap technologies and methods of fabrication 失效
标题翻译：具有嵌入式气隙技术和制造方法的背板，印刷电路板和/或多芯片模块级光学互连层
公开(公告)号：US06788867B2
公开(公告)日：2004-09-07
申请号：US10734075
申请日：2003-12-11
申请人： Tony Mule′ , James D. Meindl , Paul Kohl , Stephen M. Schultz , Thomas K. Gaylord , Elias N. Glytsis , Ricardo Villalaz , Muhannad Bakir , Hollie Reed
发明人： Tony Mule′ , James D. Meindl , Paul Kohl , Stephen M. Schultz , Thomas K. Gaylord , Elias N. Glytsis , Ricardo Villalaz , Muhannad Bakir , Hollie Reed
IPC分类号： G02B600
CPC分类号： G02B6/136 , G02B6/12004 , G02B6/132 , G02B6/138
摘要： Optical interconnect layers and methods of fabrication thereof are described. In addition, the optical interconnect layers integrated into devices such as backplane (BP), printed wiring board (PWB), and multi-chip module (MCM) level devices are described. A representative optical interconnect layer includes a first cladding layer, a second cladding layer, one or more waveguides having a waveguide core and an air-gap cladding layer engaging a portion of waveguide core, wherein the first cladding layer and the second cladding layer engage the waveguide.
摘要翻译：描述光学互连层及其制造方法。此外，描述了集成到诸如背板（BP），印刷布线板（PWB）和多芯片模块（MCM）级装置的装置中的光学互连层。代表性的光学互连层包括第一包层，第二包层，具有波导芯的一个或多个波导和与波导芯的一部分接合的气隙包层，其中第一包层和第二包层与波导。

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