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1. 发明授权

US07535907B2 TCP engine 有权
标题翻译： TCP引擎
公开(公告)号：US07535907B2
公开(公告)日：2009-05-19
申请号：US11218727
申请日：2005-09-02
申请人： Muhammad R. Hussain , Imran Badr , Faisal Masood , Philip H. Dickinson , Richard E. Kessler , Daniel A. Katz , Michael S. Bertone , Robert A. Sanzone , Thomas F. Hummel , Gregg A. Bouchard
发明人： Muhammad R. Hussain , Imran Badr , Faisal Masood , Philip H. Dickinson , Richard E. Kessler , Daniel A. Katz , Michael S. Bertone , Robert A. Sanzone , Thomas F. Hummel , Gregg A. Bouchard
IPC分类号： H04L12/28 , H04L12/56 , G06F15/16
CPC分类号： H04L69/16 , H04L49/90 , H04L49/9047 , H04L69/163
摘要： A network transport layer accelerator accelerates processing of packets so that packets can be forwarded at wire-speed. To accelerate processing of packets, the accelerator performs pre-processing on a network transport layer header encapsulated in a packet for a connection and performs in-line network transport layer checksum insertion prior to transmitting a packet. A timer unit in the accelerator schedules processing of the received packets. The accelerator also includes a free pool allocator which manages buffers for storing the received packets and a packet order unit which synchronizes processing of received packets for a same connection.
摘要翻译：网络传输层加速器加速数据包的处理，使数据包能够以线速转发。为了加速分组的处理，加速器在封装在用于连接的分组中的网络传输层报头上执行预处理，并且在发送分组之前执行在线网络传输层校验和插入。加速器中的定时器单元调度接收到的分组的处理。加速器还包括一个空闲池分配器，用于管理用于存储接收到的分组的缓冲器，以及分组顺序单元，用于同步用于相同连接的接收分组的处理。

2. 发明授权

US09596193B2 Messaging with flexible transmit ordering 有权
标题翻译：消息传递灵活的发送顺序
公开(公告)号：US09596193B2
公开(公告)日：2017-03-14
申请号：US13326091
申请日：2011-12-14
申请人： Richard E. Kessler , Thomas F. Hummel , Robert A. Sanzone , Daniel A. Katz , Michael S. Bertone
发明人： Richard E. Kessler , Thomas F. Hummel , Robert A. Sanzone , Daniel A. Katz , Michael S. Bertone
IPC分类号： H04L12/56 , H04L12/861 , H04L12/935 , H04L12/939 , H04L12/741 , H04L29/06
CPC分类号： H04L49/9057 , H04L45/74 , H04L49/3072 , H04L49/552 , H04L69/22
摘要： In one embodiment, a system includes a packet reception unit. The packet reception unit is configured to receive a packet, create a header indicating scheduling of the packet in a plurality of cores and concatenate the header and the packet. The header is based on the content of the packet. In one embodiment, a system includes a transmit silo configured to store a multiple fragments of a packet, the fragments having been sent to a destination and the transmit silo having not received an acknowledgement of receipt of the fragments from the destination. The system further includes a restriction verifier coupled with the transmit silo. The restriction verifier is configured to receive the fragments and determine whether the fragments can be sent and stored in the transmit silo.
摘要翻译：在一个实施例中，系统包括分组接收单元。分组接收单元被配置为接收分组，创建指示多个核中的分组的调度的报头，并且连接报头和分组。标题是基于数据包的内容。在一个实施例中，系统包括被配置为存储分组的多个片段的发射仓，所述片段已经被发送到目的地，并且发送仓已经没有收到来自目的地的片段接收的确认。该系统还包括与发射仓连接的限制验证器。限制验证器被配置为接收片段并且确定片段是否可以被发送并存储在传送仓中。

3. 发明申请

US20120155474A1 MESSAGING WITH FLEXIBLE TRANSMIT ORDERING 有权
标题翻译：使用灵活的发送订单进行消息传递
公开(公告)号：US20120155474A1
公开(公告)日：2012-06-21
申请号：US13326091
申请日：2011-12-14
申请人： Richard E. Kessler , Thomas F. Hummel , Robert A. Sanzone , Daniel A. Katz , Michael S. Bertone
发明人： Richard E. Kessler , Thomas F. Hummel , Robert A. Sanzone , Daniel A. Katz , Michael S. Bertone
IPC分类号： H04L12/56
CPC分类号： H04L49/9057 , H04L45/74 , H04L49/3072 , H04L49/552 , H04L69/22
摘要： In one embodiment, a system includes a packet reception unit. The packet reception unit is configured to receive a packet, create a header indicating scheduling of the packet in a plurality of cores and concatenate the header and the packet. The header is based on the content of the packet. In one embodiment, a system includes a transmit silo configured to store a multiple fragments of a packet, the fragments having been sent to a destination and the transmit silo having not received an acknowledgement of receipt of the fragments from the destination. The system further includes a restriction verifier coupled with the transmit silo. The restriction verifier is configured to receive the fragments and determine whether the fragments can be sent and stored in the transmit silo.
摘要翻译：在一个实施例中，系统包括分组接收单元。分组接收单元被配置为接收分组，创建指示多个核中的分组的调度的报头，并且连接报头和分组。标题是基于数据包的内容。在一个实施例中，系统包括被配置为存储分组的多个片段的发射仓，所述片段已经被发送到目的地，并且发送仓已经没有收到来自目的地的片段接收的确认。该系统还包括与发射仓连接的限制验证器。限制验证器被配置为接收片段并且确定片段是否可以被发送并存储在传送仓中。

4. 发明授权

US07895431B2 Packet queuing, scheduling and ordering 有权
标题翻译：分组排队，调度和排序
公开(公告)号：US07895431B2
公开(公告)日：2011-02-22
申请号：US11005490
申请日：2004-12-06
申请人： Gregg A. Bouchard , Thomas F. Hummel , Richard E. Kessler , Muhammed R. Hussain , Yen Lee
发明人： Gregg A. Bouchard , Thomas F. Hummel , Richard E. Kessler , Muhammed R. Hussain , Yen Lee
IPC分类号： H04L29/06 , H04L12/28 , G06F15/167
CPC分类号： H04L12/56 , H04L47/50 , H04L63/164 , H04L63/166
摘要： A method and apparatus for ordering, synchronizing and scheduling work in a multi-core network services processor is provided. Each piece of work is identified by a tag that indicates how the work is to be synchronized and ordered. Throughput is increased by processing work having different tags in parallel on different processor cores. Packet processing can be broken up into different phases, each phase having a different tag dependent on ordering and synchronization constraints for the phase. A tag switch operation initiated by a core switches a tag dependent on the phase. A dedicated tag switch bus minimizes latency for the tag switch operation.
摘要翻译：提供了一种用于在多核网络服务处理器中排序，同步和调度工作的方法和装置。每个工作都由一个标签标识，该标签指示工作如何同步和排序。通过在不同的处理器核心上并行处理具有不同标签的工作来增加吞吐量。分组处理可以分解成不同的阶段，每个阶段具有取决于阶段的排序和同步约束的不同标签。由核心发起的标签交换操作根据相位切换标签。专用标签交换总线最大限度地减少了标签交换操作的延迟。

5. 发明授权

US09219560B2 Multi-protocol SerDes PHY apparatus 有权
标题翻译：多协议SerDes PHY设备
公开(公告)号：US09219560B2
公开(公告)日：2015-12-22
申请号：US13280841
申请日：2011-10-25
申请人： Thomas F. Hummel
发明人： Thomas F. Hummel
IPC分类号： H04L12/28 , H04J3/04
CPC分类号： H04J3/047
摘要： In one embodiment, a multiprotocol interface includes a physical layer transmitter unit configured to transmit data from synchronous media access control layer units and asynchronous media access control layer units. The multiprotocol interface also includes a physical layer receiver unit configured to receive data and to deliver the received data to the synchronous media access control layer units and the asynchronous media access control layer units. The physical layer transmitter unit and the physical layer receiver unit are both configured to operate in either an asynchronous mode or a synchronous mode. The physical layer transmitter unit and the physical layer receiver unit transmit and receive only with the asynchronous media access control units, and physical layer transmitter unit and the physical layer receiver unit transmit and receive only with the synchronous media access control units.
摘要翻译：在一个实施例中，多协议接口包括被配置为从同步媒体访问控制层单元和异步媒体访问控制层单元传输数据的物理层发送器单元。多协议接口还包括被配置为接收数据并将接收到的数据传送到同步媒体访问控制层单元和异步媒体访问控制层单元的物理层接收器单元。物理层发射机单元和物理层接收机单元都被配置为以异步模式或同步模式操作。物理层发射机单元和物理层接收机单元仅与异步媒体接入控制单元发送和接收，物理层发射机单元和物理层接收机单元仅与同步媒体接入控制单元进行发送和接收。

6. 发明授权

US08634509B2 Synchronized clock phase interpolator 有权
标题翻译：同步时钟相位插值器
公开(公告)号：US08634509B2
公开(公告)日：2014-01-21
申请号：US13397303
申请日：2012-02-15
申请人： Ethan Crain , Thomas F. Hummel , Thucydides Xanthopoulos , Scott Meninger
发明人： Ethan Crain , Thomas F. Hummel , Thucydides Xanthopoulos , Scott Meninger
IPC分类号： H04L7/00
CPC分类号： H04L7/033 , H03L7/0807 , H03L7/0814 , H03L7/091 , H04L7/0025
摘要： A high-linearity Phase Interpolator based Clock and Data Recovery (CDR) circuit for use in a multi-standard Serializer/Deserializer (SerDes) is provided. By interpolating at a high, fixed frequency for all supported data rates and then dividing the output clock down to the appropriately frequency for each standard, the Phase Interpolator can provide for maximum phase linearity while reducing its sensitivity to noise.
摘要翻译：提供了一种用于多标准串行器/解串器（SerDes）的高线性相位插值器时钟和数据恢复（CDR）电路。通过以高固定频率对所有支持的数据速率进行内插，然后将输出时钟下降到每个标准的适当频率，相位插值器可以提供最大的相位线性度，同时降低其对噪声的敏感度。

7. 发明申请

US20130101058A1 MULTI-PROTOCOL SERDES PHY APPARATUS 有权
标题翻译：多协议服务器设备
公开(公告)号：US20130101058A1
公开(公告)日：2013-04-25
申请号：US13280841
申请日：2011-10-25
申请人： Thomas F. Hummel
发明人： Thomas F. Hummel
IPC分类号： H04L7/00 , H04L27/00
CPC分类号： H04J3/047
摘要： In one embodiment, a multiprotocol interface includes a physical layer transmitter unit configured to transmit data from synchronous media access control layer units and asynchronous media access control layer units. The multiprotocol interface also includes a physical layer receiver unit configured to receive data and to deliver the received data to the synchronous media access control layer units and the asynchronous media access control layer units. The physical layer transmitter unit and the physical layer receiver unit are both configured to operate in either an asynchronous mode or a synchronous mode. The physical layer transmitter unit and the physical layer receiver unit transmit and receive only with the asynchronous media access control units, and physical layer transmitter unit and the physical layer receiver unit transmit and receive only with the synchronous media access control units.
摘要翻译：在一个实施例中，多协议接口包括被配置为从同步媒体访问控制层单元和异步媒体访问控制层单元传输数据的物理层发送器单元。多协议接口还包括被配置为接收数据并将接收到的数据传送到同步媒体访问控制层单元和异步媒体访问控制层单元的物理层接收器单元。物理层发射机单元和物理层接收机单元都被配置为以异步模式或同步模式操作。物理层发射机单元和物理层接收机单元仅与异步媒体接入控制单元发送和接收，物理层发射机单元和物理层接收机单元仅与同步媒体接入控制单元进行发送和接收。

8. 发明申请

US20120207259A1 SYNCHRONIZED CLOCK PHASE INTERPOLATOR 有权
标题翻译：同步时钟相位控制器
公开(公告)号：US20120207259A1
公开(公告)日：2012-08-16
申请号：US13397303
申请日：2012-02-15
申请人： Ethan Crain , Thomas F. Hummel , Thucydides Xanthopoulos , Scott Meninger
发明人： Ethan Crain , Thomas F. Hummel , Thucydides Xanthopoulos , Scott Meninger
IPC分类号： H04L7/00
CPC分类号： H04L7/033 , H03L7/0807 , H03L7/0814 , H03L7/091 , H04L7/0025
摘要： A high-linearity Phase Interpolator based Clock and Data Recovery (CDR) circuit for use in a multi-standard Serializer/Deserializer (SerDes) is provided. By interpolating at a high, fixed frequency for all supported data rates and then dividing the output clock down to the appropriately frequency for each standard, the Phase Interpolator can provide for maximum phase linearity while reducing its sensitivity to noise.
摘要翻译：提供了一种用于多标准串行器/解串器（SerDes）的高线性相位插值器时钟和数据恢复（CDR）电路。通过以高固定频率对所有支持的数据速率进行内插，然后将输出时钟下降到每个标准的适当频率，相位插值器可以提供最大的相位线性度，同时降低其对噪声的敏感度。

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