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1. 发明申请

US20120207259A1 SYNCHRONIZED CLOCK PHASE INTERPOLATOR 有权
标题翻译：同步时钟相位控制器
公开(公告)号：US20120207259A1
公开(公告)日：2012-08-16
申请号：US13397303
申请日：2012-02-15
申请人： Ethan Crain , Thomas F. Hummel , Thucydides Xanthopoulos , Scott Meninger
发明人： Ethan Crain , Thomas F. Hummel , Thucydides Xanthopoulos , Scott Meninger
IPC分类号： H04L7/00
CPC分类号： H04L7/033 , H03L7/0807 , H03L7/0814 , H03L7/091 , H04L7/0025
摘要： A high-linearity Phase Interpolator based Clock and Data Recovery (CDR) circuit for use in a multi-standard Serializer/Deserializer (SerDes) is provided. By interpolating at a high, fixed frequency for all supported data rates and then dividing the output clock down to the appropriately frequency for each standard, the Phase Interpolator can provide for maximum phase linearity while reducing its sensitivity to noise.
摘要翻译：提供了一种用于多标准串行器/解串器（SerDes）的高线性相位插值器时钟和数据恢复（CDR）电路。通过以高固定频率对所有支持的数据速率进行内插，然后将输出时钟下降到每个标准的适当频率，相位插值器可以提供最大的相位线性度，同时降低其对噪声的敏感度。

2. 发明授权

US08634509B2 Synchronized clock phase interpolator 有权
标题翻译：同步时钟相位插值器
公开(公告)号：US08634509B2
公开(公告)日：2014-01-21
申请号：US13397303
申请日：2012-02-15
申请人： Ethan Crain , Thomas F. Hummel , Thucydides Xanthopoulos , Scott Meninger
发明人： Ethan Crain , Thomas F. Hummel , Thucydides Xanthopoulos , Scott Meninger
IPC分类号： H04L7/00
CPC分类号： H04L7/033 , H03L7/0807 , H03L7/0814 , H03L7/091 , H04L7/0025
摘要： A high-linearity Phase Interpolator based Clock and Data Recovery (CDR) circuit for use in a multi-standard Serializer/Deserializer (SerDes) is provided. By interpolating at a high, fixed frequency for all supported data rates and then dividing the output clock down to the appropriately frequency for each standard, the Phase Interpolator can provide for maximum phase linearity while reducing its sensitivity to noise.
摘要翻译：提供了一种用于多标准串行器/解串器（SerDes）的高线性相位插值器时钟和数据恢复（CDR）电路。通过以高固定频率对所有支持的数据速率进行内插，然后将输出时钟下降到每个标准的适当频率，相位插值器可以提供最大的相位线性度，同时降低其对噪声的敏感度。

3. 发明授权

US07961033B2 DLL-based temperature sensor 有权
标题翻译：基于DLL的温度传感器
公开(公告)号：US07961033B2
公开(公告)日：2011-06-14
申请号：US12586169
申请日：2009-09-17
申请人： Scott Meninger , Kyoungho Woo
发明人： Scott Meninger , Kyoungho Woo
IPC分类号： G05F1/10
CPC分类号： H03L7/0812
摘要： A temperature sensor includes an open-loop delay line comprising plural delay cells and a multiplexer configured to select a first number of the plural delay cells; a delay-locked loop comprising plural delay cells and a multiplexer configured to select a second number of the plural delay cells; a clock coupled to an input of the open-loop delay line and to an input of the delay-locked loop; a detector having a first input coupled to an output of the open-loop delay line and a second input coupled to an output of the delay-locked loop; and a finite state machine configured to detect a transition in the output of the phase detector.
摘要翻译：温度传感器包括：开环延迟线，包括多个延迟单元;多路复用器，被配置为选择多个延迟单元的第一数量; 延迟锁定环路，包括多个延迟单元和被配置为选择所述多个延迟单元的第二数量的多路复用器; 耦合到开环延迟线的输入和延迟锁定环的输入的时钟; 检测器，其具有耦合到所述开环延迟线的输出的第一输入和耦合到所述延迟锁定环的输出的第二输入; 以及被配置为检测相位检测器的输出中的转变的有限状态机。

4. 发明申请

US20100141328A1 DLL-based temperature sensor 有权
标题翻译：基于DLL的温度传感器
公开(公告)号：US20100141328A1
公开(公告)日：2010-06-10
申请号：US12586169
申请日：2009-09-17
申请人： Scott Meninger , Kyoungho Woo
发明人： Scott Meninger , Kyoungho Woo
IPC分类号： H01L35/00
CPC分类号： H03L7/0812
摘要： A temperature sensor includes an open-loop delay line comprising plural delay cells and a multiplexer configured to select a first number of the plural delay cells; a delay-locked loop comprising plural delay cells and a multiplexer configured to select a second number of the plural delay cells; a clock coupled to an input of the open-loop delay line and to an input of the delay-locked loop; a detector having a first input coupled to an output of the open-loop delay line and a second input coupled to an output of the delay-locked loop; and a finite state machine configured to detect a transition in the output of the phase detector.
摘要翻译：温度传感器包括：开环延迟线，包括多个延迟单元;多路复用器，被配置为选择多个延迟单元的第一数量; 延迟锁定环路，包括多个延迟单元和被配置为选择所述多个延迟单元的第二数量的多路复用器; 耦合到开环延迟线的输入和延迟锁定环的输入的时钟; 检测器，其具有耦合到所述开环延迟线的输出的第一输入和耦合到所述延迟锁定环的输出的第二输入; 以及被配置为检测相位检测器的输出中的转变的有限状态机。

5. 发明申请

US20050094757A1 Method and apparatus for reducing quantization noise in fractional-N frequency synthesizers 有权
$Method and apparatus for reducing quantization noise in fractional-N frequency synthesizers$
标题翻译：分数N频率合成器中减少量化噪声的方法和装置
公开(公告)号：US20050094757A1
公开(公告)日：2005-05-05
申请号：US10701732
申请日：2003-11-05
申请人： Scott Meninger , Michael Perrott
发明人： Scott Meninger , Michael Perrott
IPC分类号： H03D3/24 , H03L7/087 , H03L7/089 , H03L7/197
CPC分类号： H03L7/1976 , H03L7/087 , H03L7/0898
摘要： Described are methods and modules for reducing the phase noise generated in a fractional-N frequency synthesizer. The methods are based on swapping phase signals to achieve the same average delay for each phase signal path, compensation and resynchronization of phase signals and shuffling of digital-to-analog unit elements used to produce specific quantization levels. One method is based on digital gain compensation used to correct for frequency-dependent error arising from differences between horizontal slicing quantization techniques and conventional vertical slicing techniques. Also described are a combined phase detector and DAC module and a method for extending its range.
摘要翻译：描述了用于减小分数N频率合成器中产生的相位噪声的方法和模块。这些方法基于交换相位信号，以实现每个相位信号路径的相同平均延迟，相位信号的补偿和重新同步以及用于产生特定量化电平的数模转换单元的混洗。一种方法是基于用于校正由水平切片量化技术和常规垂直切片技术之间的差异引起的频率相关误差的数字增益补偿。还描述了组合相位检测器和DAC模块以及用于扩展其范围的方法。

6. 发明授权

US08519785B2 Differential amplifier with duty cycle compensation 有权
标题翻译：带占空比补偿的差分放大器
公开(公告)号：US08519785B2
公开(公告)日：2013-08-27
申请号：US13369562
申请日：2012-02-09
申请人： Scott Meninger
发明人： Scott Meninger
IPC分类号： H03F3/45
CPC分类号： H03F1/3223 , H03F2203/45138
摘要： A differential amplifier replicates the input stage and cross-connects the inputs, so that the input-to-output delay will be balanced in an averaged sense. The outputs of each of the two input stages are then summed after an open loop delay matched inversion has taken place. The result is a reduction in the duty cycle distortion of the receiver amplifier over process voltage and temperature (PVT) variation. This is enabled by the fact that a full swing CMOS delay cell can be made to have good delay matching over PVT, whereas the input stage to a differential amplifier may, depending on architecture, have poor delay matching because of impedance mismatches within the amplifier.
摘要翻译：差分放大器复制输入级并交叉连接输入，使得输入到输出延迟将以平均意义平衡。然后，在开环延迟匹配反转发生之后，两个输入级中的每一个的输出相加。结果是接收机放大器的工作电压和温度（PVT）变化的占空比失真减小。这可以通过以下事实实现：可以使全摆幅CMOS延迟单元在PVT上具有良好的延迟匹配，而根据架构，差分放大器的输入级可能由于放大器内的阻抗失配而具有差的延迟匹配。

7. 发明申请

US20120206198A1 DIFFERENTIAL AMPLIFIER WITH DUTY CYCLE COMPENSATION 有权
标题翻译：具有占空比补偿的差分放大器
公开(公告)号：US20120206198A1
公开(公告)日：2012-08-16
申请号：US13369562
申请日：2012-02-09
申请人： Scott Meninger
发明人： Scott Meninger
IPC分类号： H03F3/45
CPC分类号： H03F1/3223 , H03F2203/45138
摘要： A differential amplifier replicates the input stage and cross-connects the inputs, so that the input-to-output delay will be balanced in an averaged sense. The outputs of each of the two input stages are then summed after an open loop delay matched inversion has taken place. The result is a reduction in the duty cycle distortion of the receiver amplifier over process voltage and temperature (PVT) variation. This is enabled by the fact that a full swing CMOS delay cell can be made to have good delay matching over PVT, whereas the input stage to a differential amplifier may, depending on architecture, have poor delay matching because of impedance mismatches within the amplifier.
摘要翻译：差分放大器复制输入级并交叉连接输入，使得输入到输出延迟将以平均意义平衡。然后，在开环延迟匹配反转发生之后，两个输入级中的每一个的输出相加。结果是接收机放大器的工作电压和温度（PVT）变化的占空比失真减小。这可以通过以下事实实现：可以使全摆幅CMOS延迟单元在PVT上具有良好的延迟匹配，而根据架构，差分放大器的输入级可能由于放大器内的阻抗失配而具有差的延迟匹配。

8. 发明申请

US20090058529A1 Resistively Loaded Single Stage Differential Amplifier Having Zero Volt Common Mode Input 有权
标题翻译：具有零伏共模输入的电阻式单级差分放大器
公开(公告)号：US20090058529A1
公开(公告)日：2009-03-05
申请号：US11849122
申请日：2007-08-31
申请人： Scott Meninger
发明人： Scott Meninger
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , H03F3/45179 , H03F3/45192 , H03F3/45636 , H03F3/45744 , H03F2203/45008 , H03F2203/45134 , H03F2203/45306 , H03F2203/45384 , H03F2203/45392 , H03F2203/45544
摘要： A resistively folded single stage differential amplifier capable of accommodating a low input common mode without impacting the performance of a bias current source, while also providing a high input impedance to allow for the use of the linear termination resistors. The differential amplifier provides an amplified output signal with a common mode referenced to an upper bound of an input power supply. The differential amplifier includes an input sub-stage and a transistor sub-stage resistively folding the input sub-stage.
摘要翻译：一种电阻折叠单级差分放大器，能够适应低输入共模而不影响偏置电流源的性能，同时还提供高输入阻抗以允许使用线性终端电阻。差分放大器提供以与输入电源的上限为基准的共模的放大输出信号。差分放大器包括输入子级和晶体管子级，电阻地折叠输入子级。

9. 发明授权

US08471601B2 Single-ended to differential converter 有权
公开(公告)号：US08471601B2
公开(公告)日：2013-06-25
申请号：US12214789
申请日：2008-06-20
申请人： Scott Meninger
发明人： Scott Meninger
IPC分类号： H03K3/00
CPC分类号： H03K5/02 , H03K19/0175
摘要： A single-ended to differential converter is presented. The converter may be configured to convert full-swing single-ended signals to low-swing differential signals within a single-stage, thereby reducing signal distortion. The converter may include a passive network of resistive elements, for example resistors and/or metal oxide semiconductor (MOS) devices operating in a linear region. The converter may also allow for adjustable design parameters such as a common mode, differential amplitude, and an output swing. The adjustments may all be made within the single-stage of the converter.

10. 发明申请

US20090315602A1 Single-ended to differential converter 有权
标题翻译：单端到差分转换器
公开(公告)号：US20090315602A1
公开(公告)日：2009-12-24
申请号：US12214789
申请日：2008-06-20
申请人： Scott Meninger
发明人： Scott Meninger
IPC分类号： H03K5/02
CPC分类号： H03K5/02 , H03K19/0175
摘要： A single-ended to differential converter is presented. The converter may be configured to convert full-swing single-ended signals to low-swing differential signals within a single-stage, thereby reducing signal distortion. The converter may include a passive network of resistive elements, for example resistors and/or metal oxide semiconductor (MOS) devices operating in a linear region. The converter may also allow for adjustable design parameters such as a common mode, differential amplitude, and an output swing. The adjustments may all be made within the single-stage of the converter.
摘要翻译：提出了一个单端到差分转换器。转换器可以被配置为将全摆幅单端信号转换成单级中的低摆幅差分信号，从而减少信号失真。转换器可以包括电阻元件的无源网络，例如在线性区域中操作的电阻器和/或金属氧化物半导体（MOS）器件。转换器还可以允许可调整的设计参数，例如共模，差分幅度和输出摆幅。调整可以在转换器的单级中进行。

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