专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20100081278A1 Methods for Nanoscale Feature Imprint Molding 失效
标题翻译：纳米特征压印成型方法
公开(公告)号：US20100081278A1
公开(公告)日：2010-04-01
申请号：US11467822
申请日：2006-08-28
申请人： Muhammad Mustafa Hussain , Naim Moumen , Gabriel Gebara , Ed Labelle , Sidi Lanee , Barry Sassman , Raj Jammy
发明人： Muhammad Mustafa Hussain , Naim Moumen , Gabriel Gebara , Ed Labelle , Sidi Lanee , Barry Sassman , Raj Jammy
IPC分类号： H01L21/768 , H01L21/30
CPC分类号： G03F7/0002 , B82Y10/00 , B82Y40/00 , H01L29/0665 , H01L29/0673 , Y10S977/887 , Y10S977/888
摘要： Methods for fabricating nanoscale features are disclosed. One technique involves depositing onto a substrate, where the first layer may be a silicon layer and may subsequently be etched. A second layer and third layer may be deposited on the etch first layer, followed by the deposition of a silicon cap. The second and third layer may be etched, exposing edges of the second and third layers. The cap and first layer may be removed and either the second or third layer may be etched, creating a nanoscale pattern.
摘要翻译：公开了制造纳米级特征的方法。一种技术涉及沉积到衬底上，其中第一层可以是硅层并随后被蚀刻。第二层和第三层可以沉积在蚀刻第一层上，随后沉积硅帽。可以蚀刻第二层和第三层，暴露第二层和第三层的边缘。盖和第一层可以被去除并且可以蚀刻第二层或第三层，产生纳米尺度图案。

2. 发明授权

US07736954B2 Methods for nanoscale feature imprint molding 失效
标题翻译：纳米级特征压印成型方法
公开(公告)号：US07736954B2
公开(公告)日：2010-06-15
申请号：US11467822
申请日：2006-08-28
申请人： Muhammad Mustafa Hussain , Naim Moumen , Gabriel Gebara , Ed Labelle , Sidi Lanee , Barry Sassman , Raj Jammy
发明人： Muhammad Mustafa Hussain , Naim Moumen , Gabriel Gebara , Ed Labelle , Sidi Lanee , Barry Sassman , Raj Jammy
IPC分类号： H01L21/84
CPC分类号： G03F7/0002 , B82Y10/00 , B82Y40/00 , H01L29/0665 , H01L29/0673 , Y10S977/887 , Y10S977/888
摘要： Methods for fabricating nanoscale features are disclosed. One technique involves depositing onto a substrate, where the first layer may be a silicon layer and may subsequently be etched. A second layer and third layer may be deposited on the etch first layer, followed by the deposition of a silicon cap. The second and third layer may be etched, exposing edges of the second and third layers. The cap and first layer may be removed and either the second or third layer may be etched, creating a nanoscale pattern.
摘要翻译：公开了制造纳米级特征的方法。一种技术涉及沉积到衬底上，其中第一层可以是硅层并随后被蚀刻。第二层和第三层可以沉积在蚀刻第一层上，随后沉积硅帽。可以蚀刻第二层和第三层，暴露第二层和第三层的边缘。盖和第一层可以被去除并且可以蚀刻第二层或第三层，产生纳米尺度图案。

3. 发明申请

US20070059874A1 Dual Metal Gate and Method of Manufacture 审中-公开
标题翻译：双金属门和制造方法
公开(公告)号：US20070059874A1
公开(公告)日：2007-03-15
申请号：US11456054
申请日：2006-07-06
申请人： Naim Moumen , Husam Alshareef , Joel Barnett , Muhammad Hussain , Hongfa Luan , Seung-Chul Song , Raj Jammy
发明人： Naim Moumen , Husam Alshareef , Joel Barnett , Muhammad Hussain , Hongfa Luan , Seung-Chul Song , Raj Jammy
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842
摘要： Methods for fabricating two metal gate stacks for complementary metal oxide semiconductor (CMOS) devices are provided. A common layer, such as a metal layer, a metal alloy layer, or a metal nitride layer may be deposited on to a gate dielectric. A first mask layer may be deposited and patterned over an active region, exposing a portion of the common layer. A first ion may be deposited in the common layer forming a first mask layer. Similarly, a second mask layer may be deposited and patterned over the other active region and the first metal layer, and another portion of the common layer is exposed. A second ion may be deposited in the common layer, forming a second mask layer.
摘要翻译：提供了用于制造用于互补金属氧化物半导体（CMOS）器件的两个金属栅极叠层的方法。诸如金属层，金属合金层或金属氮化物层的公共层可以沉积到栅极电介质上。可以在有源区上沉积和图案化第一掩模层，暴露公共层的一部分。可以在形成第一掩模层的公共层中沉积第一离子。类似地，第二掩模层可以在另一个有源区和第一金属层上沉积和图案化，并且公共层的另一部分被暴露。可以在公共层中沉积第二离子，形成第二掩模层。

4. 发明授权

US06605860B1 Semiconductor structures and manufacturing methods 有权
标题翻译：半导体结构及制造方法
公开(公告)号：US06605860B1
公开(公告)日：2003-08-12
申请号：US09597442
申请日：2000-06-20
申请人： Helmut Horst Tews , Alexander Michaelis , Stephan Kudelka , Uwe Schroeder , Raj Jammy , Ulrike Gruening
发明人： Helmut Horst Tews , Alexander Michaelis , Stephan Kudelka , Uwe Schroeder , Raj Jammy , Ulrike Gruening
IPC分类号： H01L2906
CPC分类号： H01L21/28202 , H01L21/02164 , H01L21/0217 , H01L21/0223 , H01L21/02238 , H01L21/02247 , H01L21/02255 , H01L21/2822 , H01L21/3144 , H01L21/31658 , H01L27/10864 , H01L29/045 , H01L29/42368 , H01L29/512 , H01L29/513 , H01L29/518 , H01L29/66666 , H01L29/7827 , Y10S257/905
摘要： A method for forming substantially uniformly thick, thermally grown, silicon dioxide material on a silicon body independent of bon axis. A trench is formed in a surface of the silicon body, such trench having sidewalls disposed in different crystallographic planes, one of such planes being the crystallographic plane and another one of such planes being the plane. A substantially uniform layer of silicon nitride is formed on the sidewalls. The trench, with the with substantially uniform layer of silicon nitride, is subjected to a silicon oxidation environment with sidewalls in the plane being oxidized at a higher rate than sidewalls in the plane producing silicon dioxide on the silicon nitride layer having thickness over the plane greater than over the plane. The silicon dioxide is subjected to an etch to selectively remove silicon dioxide while leaving substantially un-etched silicon nitride to thereby remove portions of the silicon dioxide over the plane and to thereby expose underlying portions of the silicon nitride material while leaving portions of the silicon dioxide over the plane on underlying portions of the silicon nitride material. Exposed portions of the silicon nitride material are selectively removed to expose underlying portions of the sidewalls of the trench disposed in the plane while leaving substantially un-etched portions of the silicon nitride material disposed on sidewalls of the trench disposed in the plane. The structure is then subjected to an silicon oxidation environment to produce the substantially uniform silicon dioxide layer on the sidewalls of the trench.
摘要翻译：一种在硅主体上形成基本上均匀的厚的热生长二氧化硅材料的方法，其独立于凸轮轴。沟槽形成在硅体的表面中，这样的沟槽具有设置在不同结晶平面中的侧壁，这些平面中的一个是100晶体平面，另外一个这样的平面是“10”平面。在侧壁上形成基本均匀的氮化硅层。具有基本上均匀的氮化硅层的沟槽经受硅氧化环境，其中<110>面中的侧壁以比在100平面中的侧壁更高的速率被氧化，在氮化硅层上产生二氧化硅具有比<110>平面上的厚度大于超过<100>平面的厚度。对二氧化硅进行蚀刻以选择性地去除二氧化硅，同时留下基本未蚀刻的氮化硅，从而在<100>平面上除去二氧化硅的一部分，从而暴露氮化硅材料的下面部分，同时留下部分在氮化硅材料的下面部分上的<110>面上的二氧化硅。选择性地去除氮化硅材料的暴露部分以暴露设置在<100>平面中的沟槽的侧壁的下面部分，同时留下设置在设置在<110>平面中的沟槽的侧壁上的氮化硅材料的基本上未蚀刻的部分 >飞机。然后将该结构进行硅氧化环境以在沟槽的侧壁上产生基本均匀的二氧化硅层。

5. 发明授权

US06740555B1 Semiconductor structures and manufacturing methods 有权
标题翻译：半导体结构及制造方法
公开(公告)号：US06740555B1
公开(公告)日：2004-05-25
申请号：US09408248
申请日：1999-09-29
申请人： Helmut Horst Tews , Alexander Michaelis , Stephan Kudelka , Uwe Schroeder , Raj Jammy , Ulrike Gruening
发明人： Helmut Horst Tews , Alexander Michaelis , Stephan Kudelka , Uwe Schroeder , Raj Jammy , Ulrike Gruening
IPC分类号： H01L218242
CPC分类号： H01L21/28202 , H01L21/02164 , H01L21/0217 , H01L21/0223 , H01L21/02238 , H01L21/02247 , H01L21/02255 , H01L21/2822 , H01L21/3144 , H01L21/31658 , H01L27/10864 , H01L29/045 , H01L29/42368 , H01L29/512 , H01L29/513 , H01L29/518 , H01L29/66666 , H01L29/7827 , Y10S257/905
摘要： A method for forming substantially uniformly thick, thermally grown, silicon dioxide material on a silicon body independent of axis. A trench is formed in a surface of the silicon body, such trench having sidewalls disposed in different crystallographic planes, one of such planes being the crystallographic plane and another one of such planes being the plane. A substantially uniform layer of silicon nitride is formed on the sidewalls. The trench, with the substantially uniform layer of silicon nitride, is subjected to a silicon oxidation environment with sidewalls in the plane being oxidized at a higher rate than sidewalls in the plane producing silicon dioxide on the silicon nitride layer having thickness over the plane greater than over the plane. The silicon dioxide is subjected to an etch to selectively remove silicon dioxide while leaving substantially un-etched silicon nitride to thereby remove portions of the silicon dioxide over the plane and to thereby expose underlying portions of the silicon nitride material while leaving portions of the silicon dioxide over the plane on underlying portions of the silicon nitride material. Exposed portions of the silicon nitride material are selectively removed to expose underlying portions of the sidewalls of the trench disposed in the plane while leaving substantially un-etched portions of the silicon nitride material disposed on sidewalls of the trench disposed in the plane. The structure is then subjected to an silicon oxidation environment to produce the substantially uniform silicon dioxide layer on the sidewalls of the trench.
摘要翻译：一种用于在独立于轴的硅体上形成基本上均匀的厚的，热生长的二氧化硅材料的方法。沟槽形成在硅体的表面中，这种沟槽具有设置在不同结晶平面内的侧壁，其中一个这样的平面是<100>结晶平面，另外一个这样的平面是<110>平面。在侧壁上形成基本均匀的氮化硅层。具有基本上均匀的氮化硅层的沟槽经受硅氧化环境，其中<110>面中的侧壁以比在100平面中的侧壁更高的速率被氧化，在氮化硅层上产生二氧化硅，厚度大于<100>平面上的厚度。对二氧化硅进行蚀刻以选择性地去除二氧化硅，同时留下基本未蚀刻的氮化硅，从而在<100>平面上除去二氧化硅的一部分，从而暴露氮化硅材料的下面部分，同时留下部分在氮化硅材料的下面部分上的<110>面上的二氧化硅。选择性地去除氮化硅材料的暴露部分以暴露设置在<100>平面中的沟槽的侧壁的下面部分，同时留下设置在设置在<110>平面中的沟槽的侧壁上的氮化硅材料的基本上未蚀刻的部分 >飞机。然后将该结构进行硅氧化环境以在沟槽的侧壁上产生基本均匀的二氧化硅层。

6. 发明授权

US06451662B1 Method of forming low-leakage on-chip capacitor 失效
标题翻译：形成低漏电片上电容器的方法
公开(公告)号：US06451662B1
公开(公告)日：2002-09-17
申请号：US09970635
申请日：2001-10-04
申请人： Michael Chudzik , Oleg Gluschenkov , Raj Jammy , Uwe Schroeder , Helmut Tews
发明人： Michael Chudzik , Oleg Gluschenkov , Raj Jammy , Uwe Schroeder , Helmut Tews
IPC分类号： H01L2120
CPC分类号： H01L27/10861 , H01L21/02164 , H01L21/0217 , H01L21/02247 , H01L21/02255 , H01L21/02271 , H01L21/02326 , H01L21/02332 , H01L21/02337 , H01L21/0234 , H01L21/31662 , H01L21/32105
摘要： An improved capacitor is formed by a process where an improved node dielectric layer is formed with an improved dielectric constant by performing an Free Radical Enhanced Rapid Thermal Oxidation (FRE RTO) step during formation of the node dielectric layer. Use of an FRE RTO step instead of the conventional furnace oxidation step produces a cleaner oxide with a higher dielectric constant and higher capacitance. Other specific embodiments of the invention include improved node dielectric layer by one or more additional nitridation steps, done by either Remote Plasma Nitridation (RPN), Rapid Thermal Nitridation (RTN), Decoupled Plasma Nitridation (DPN) or other nitridation method; selective oxidation; use of a metal layer rather than a SiN layer as the dielectric base; and selective oxidation of the metal layer.
摘要翻译：通过在形成节点介质层期间通过执行自由基增强快速热氧化（FRE RTO）步骤而改进的介电常数形成改进的节点电介质层的工艺形成改进的电容器。使用FRE RTO步骤代替常规炉氧化步骤产生具有更高介电常数和较高电容的清洁氧化物。本发明的其它具体实施方案包括通过远程等离子体氮化（RPN），快速热氮化（RTN），去耦等离子体氮化（DPN）或其它氮化方法进行的一个或多个另外的氮化步骤改进的节点电介质层; 选择性氧化; 使用金属层而不是SiN层作为电介质基底; 和金属层的选择性氧化。

7. 发明授权

US06362040B1 Reduction of orientation dependent oxidation for vertical sidewalls of semiconductor substrates 失效
标题翻译：减少半导体衬底的垂直侧壁的取向依赖氧化
公开(公告)号：US06362040B1
公开(公告)日：2002-03-26
申请号：US09501502
申请日：2000-02-09
申请人： Helmut Horst Tews , Brian S. Lee , Ulrike Gruening , Raj Jammy , John Faltermeier
发明人： Helmut Horst Tews , Brian S. Lee , Ulrike Gruening , Raj Jammy , John Faltermeier
IPC分类号： H01L218242
CPC分类号： H01L27/10864 , H01L21/02238 , H01L21/02255 , H01L21/02299 , H01L21/31662 , H01L27/10876
摘要： A method for growing a dielectric layer on a substrate, in accordance with the present invention, includes the steps of providing a substrate having at least two crystallographic planes which experience different dielectric layer growth rates due to the at least two crystallographic planes. A first dielectric layer is grown on the at least two crystallographic planes such that the first dielectric layer has a first thickness on a first crystallographic plane and a second thickness on a second crystallographic plane. The first thickness is thicker than the second thickness for the first dielectric layer. Dopants are implanted through the first dielectric layer. A greater number of dopants are implanted in the substrate through the second thickness than through the first thickness of the first dielectric layer. The first dielectric layer is then removed. A second dielectric layer is grown at a same location as the removed first dielectric layer. The second dielectric layer has a first thickness on a first crystallographic plane and a second thickness on a second crystallographic plane. The first thickness and the second thickness of the second dielectric layer are closer in thickness than the first thickness and the second thickness of the first dielectric layer due to the implantation of the dopants.
摘要翻译：根据本发明的用于在衬底上生长电介质层的方法包括以下步骤：提供具有至少两个结晶面的衬底，所述晶体面由于至少两个晶面而具有不同的介电层生长速率。在至少两个晶面上生长第一介电层，使得第一介电层在第一结晶平面上具有第一厚度，在第二结晶平面上具有第二厚度。第一厚度比第一电介质层的第二厚度厚。通过第一介电层注入掺杂剂。通过第二厚度将更多数量的掺杂剂注入到衬底中，而不是通过第一介电层的第一厚度。然后去除第一介电层。在与去除的第一介电层相同的位置处生长第二介电层。第二电介质层在第一结晶平面上具有第一厚度，在第二结晶平面上具有第二厚度。由于掺杂剂的注入，第二介电层的第一厚度和第二厚度比第一厚度和第一介电层的第二厚度更厚。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式