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1. 发明授权

US08719756B2 Power grid mosaicing with deep-sub-tile cells 有权
标题翻译：电网拼接与深层细胞
公开(公告)号：US08719756B2
公开(公告)日：2014-05-06
申请号：US13267081
申请日：2011-10-06
申请人： Mu-Jing Li , Timothy Johnson
发明人： Mu-Jing Li , Timothy Johnson
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： A computer aided design system can determine coverage of a metal layer mosaic. The system can apply a tile pattern to a design including at least one layer. Then, the system can identify at least one tile of the tile pattern that violates at least one first design rule. After that, the system can apply a sub-tile pattern to an area identified in the identifying the at least one tile of the tile pattern that violates the design rule. The system further can identify at least one sub-tile of the sub-tile pattern that violates at least one second design rule. Finally, the system can apply a deep-sub-tile pattern to an area identified in the identifying the at least one sub-tile of the sub-tile pattern that violates the second design rule.
摘要翻译：计算机辅助设计系统可以确定金属层镶嵌的覆盖范围。该系统可以将瓦片图案应用于包括至少一层的设计。然后，系统可以识别违反至少一个第一设计规则的瓦片图案的至少一个瓦片。之后，系统可以将子块图案应用于在识别违反设计规则的瓦片图案的至少一个瓦片中识别的区域。该系统还可以识别违反至少一个第二设计规则的子瓦片图案的至少一个子瓦片。最后，系统可以将深层次图案应用于在识别违反第二设计规则的子图案图案的至少一个子图块中识别的区域。

2. 发明授权

US07096447B1 Method and apparatus for efficiently locating and automatically correcting certain violations in a complex existing circuit layout 有权
标题翻译：用于在复杂的现有电路布局中有效定位和自动校正某些违规的方法和装置
公开(公告)号：US07096447B1
公开(公告)日：2006-08-22
申请号：US10686471
申请日：2003-10-15
申请人： Mu-Jing Li , Suryanarayana R. Maturi , Pankaj Dixit
发明人： Mu-Jing Li , Suryanarayana R. Maturi , Pankaj Dixit
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： An exemplary CAD design flow modifies an existing large scale chip layout to reinforce the redundant via design rules to improve the yield and reliability. The flow operates on each metal-via pair from bottom up to locate and correct isolated via rule violations by adding metal features and vias in a respective patch cell associated with each cluster cell. A large complex design is thus divided into cells so that multiple processes can work concurrently as if every process were working on the top level of the design layout.
摘要翻译：示例性CAD设计流程修改现有的大规模芯片布局以加强冗余通路设计规则以提高产量和可靠性。每个金属通孔对从下往上运行，通过在与每个聚集单元相关联的相应补丁单元中添加金属特征和通孔来定位和校正隔离的规则违规。因此，将大型复杂设计分为单元格，以便多个进程同时工作，就好像每个进程在设计布局的顶层工作一样。

3. 发明授权

US06871332B2 Structure and method for separating geometries in a design layout into multi-wide object classes 有权
标题翻译：将设计布局中的几何形状分离成多宽对象类的结构和方法
公开(公告)号：US06871332B2
公开(公告)日：2005-03-22
申请号：US10260813
申请日：2002-09-30
申请人： Mu-Jing Li , Amy Yang
发明人： Mu-Jing Li , Amy Yang
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Manipulation of a multi-wide object class design layout to facilitate design rule checking or automatic correction of design rule errors is improved by deriving wide class objects from geometries of the design layout, and applying certain rules to non-virtual boundaries of the wide class objects that are not applied to virtual boundaries of the wide class objects. In an exemplary embodiment, the wide class objects are preferably derived by sizing down, then sizing up, each geometry by a sizing factor equal to half the minimum width of the particular wide class object less an amount that preferably corresponds to that represented by a minimum resolution of the design layout. Portions of a geometry that are otherwise excluded as being too narrow in width, but that lie wholly within a correction factor of the boundary of the wide class object otherwise derived, are preferably included to form effective wide class objects.
摘要翻译：通过从设计布局的几何导出宽类对象并将某些规则应用于宽类对象的非虚拟边界，可以改进多广度对象类设计布局的操纵以促进设计规则检查或设计规则错误的自动校正它们不会应用于宽类对象的虚拟边界。在示例性实施例中，宽类对象优选地通过将每个几何尺寸调整大小，然后通过等于特定宽类对象的最小宽度的一半的尺寸因子来调整尺寸，然后将其优选地对应于由最小值分辨率的设计布局。否则被排除为宽度过窄但完全位于另外导出的宽类对象的边界的校正因子内的几何的部分优选地被包括以形成有效的宽类对象。

4. 发明授权

US08423943B2 Self-propelling decoupling capacitor design for flexible area decoupling capacitor fill design flow 有权
标题翻译：自推进去耦电容设计，用于灵活区域去耦电容填充设计流程
公开(公告)号：US08423943B2
公开(公告)日：2013-04-16
申请号：US13343632
申请日：2012-01-04
申请人： Mu-Jing Li
发明人： Mu-Jing Li
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method of filling dcaps in an integrated circuit includes identifying a set of dcap-eligible areas of the integrated circuit for areas large enough to accommodate at least one dcap cell having a selected size smaller than a default size. The dcap cell includes at least one built-in power track. A set of dcap cells are filled in the identified set of dcap-eligible areas. Each of the built-in power tracks included in the set of dcap cells is connected to a corresponding power grid. An integrated circuit including a power grid channel formed between at least two power grids and a plurality of dcaps including a first dcap included in a dcap cell, the dcap cell including built-in power tracks, each one of the built-in power tracks being connected to a corresponding one of the at least two power grids is also described.
摘要翻译：一种在集成电路中填充dcap的方法包括：为足以容纳具有小于默认尺寸的所选尺寸的至少一个dcap单元的区域，识别集成电路的一组dcap符合区域。 dcap单元包括至少一个内置的电源轨。一组dcap电池被填充在所识别的一组dcap符合条件的区域中。包括在一组dcap单元中的每个内置电源轨都连接到相应的电网。一种集成电路，包括形成在至少两个电网之间的电网通道和包括在dcap单元中的第一dcap的多个dcap，所述dcap单元包括内置电力轨道，每个所述内置电力轨道为还描述了连接到至少两个电网中的对应的一个电网。

5. 发明授权

US08117581B1 Self-propelling decoupling capacitor design for flexible area decoupling capacitor fill design flow 有权
标题翻译：自推进去耦电容设计，用于灵活区域去耦电容填充设计流程
公开(公告)号：US08117581B1
公开(公告)日：2012-02-14
申请号：US11449057
申请日：2006-06-07
申请人： Mu-Jing Li
发明人： Mu-Jing Li
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method of filling dcaps in an integrated circuit includes identifying a set of dcap-eligible areas of the integrated circuit for areas large enough to accommodate at least one dcap cell having a selected size smaller than a default size. The dcap cell includes at least one built-in power track. A set of dcap cells are filled in the identified set of dcap-eligible areas. Each of the built-in power tracks included in the set of dcap cells is connected to a corresponding power grid. An integrated circuit including a power grid channel formed between at least two power grids and a plurality of dcaps including a first dcap included in a dcap cell, the dcap cell including built-in power tracks, each one of the built-in power tracks being connected to a corresponding one of the at least two power grids is also described.
摘要翻译：一种在集成电路中填充dcap的方法包括：为足以容纳具有小于默认尺寸的所选尺寸的至少一个dcap单元的区域，识别集成电路的一组dcap符合区域。 dcap单元包括至少一个内置的电源轨。一组dcap电池被填充在所识别的一组dcap符合条件的区域中。包括在一组dcap单元中的每个内置电源轨都连接到相应的电网。一种集成电路，包括形成在至少两个电网之间的电网通道和包括在dcap单元中的第一dcap的多个dcap，所述dcap单元包括内置电力轨道，每个所述内置电力轨道为还描述了连接到至少两个电网中的对应的一个电网。

6. 发明申请

US20070300195A1 METHOD AND COMPUTER PROGRAM PRODUCT FOR INTERLAYER CONNECTION OF ARBITRARILY COMPLEX SHAPES UNDER ASYMMETRIC VIA ENCLOSURE RULES 有权
标题翻译：方法和计算机程序产品用于通过外壳规则不对称的仲裁复合形式的层间连接
公开(公告)号：US20070300195A1
公开(公告)日：2007-12-27
申请号：US11426223
申请日：2006-06-23
申请人： Mu-Jing Li
发明人： Mu-Jing Li
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5077
摘要： In some embodiments, a method is provided for determining a localized region of overlap of first and second features from respective first and second conductive layers, and determining which enclosure rules to apply to vias formed between the first and second features. In a further aspect of the invention, a method may be provided to determine whether to apply symmetric or asymmetric via metal enclosure rules to a feature as a function of the local environment of the feature. In another aspect of the invention, a computer program product is provided to encode instructions for performing such a process.
摘要翻译：在一些实施例中，提供了一种用于从相应的第一和第二导电层确定第一和第二特征的重叠的局部区域的方法，以及确定应用于在第一和第二特征之间形成的通孔的哪些外壳规则。在本发明的另一方面，可以提供一种方法来确定是否将对称或不对称的金属外壳规则应用于特征，作为特征的局部环境的函数。在本发明的另一方面，提供了一种计算机程序产品来编码用于执行这种处理的指令。

7. 发明授权

US06735749B2 (Design rule check)/(electrical rule check) algorithms using a system resolution 有权
标题翻译：（设计规则检查）/（电气规则检查）算法使用系统分辨率
公开(公告)号：US06735749B2
公开(公告)日：2004-05-11
申请号：US10103521
申请日：2002-03-21
申请人： Mu-Jing Li , Amy Yang
发明人： Mu-Jing Li , Amy Yang
IPC分类号： G06F1750
CPC分类号： G06F17/5081
摘要： Method and apparatus for checking integrated circuit designs. In particular, one embodiment of the present invention is a method that for checking integrated circuit design files using (design rule check)/(electrical rule check) files (DRC/ERC files) wherein design objects are disposed on a grid having a system resolution, the method comprising steps of: (a) growing one or more rectangular boxes having at least two sides of length equal to the system resolution outward or inward from one or more of an edge of a design object and a side of a design object; (b) performing one or more of a spacing DRC/ERC check and an overlay DRC/ERC check; and (c) identifying checks relating to the rectangular boxes.
摘要翻译：用于检查集成电路设计的方法和装置。特别地，本发明的一个实施例是一种使用（设计规则检查）/（电气规则检查）文件（DRC / ERC文件）来检查集成电路设计文件的方法，其中设计对象被布置在具有系统分辨率的网格上该方法包括以下步骤：（a）从设计对象的边缘和设计对象的一侧的一个或多个边缘生长一个或多个矩形框，其具有至少两边的长度等于系统分辨率的向外或向内; （b）执行间隔DRC / ERC检查和覆盖DRC / ERC检查中的一个或多个; 和（c）识别与矩形框有关的检查。

8. 发明授权

US06915252B1 Method and system for ensuring consistency of design rule application in a CAD environment 有权
标题翻译：确保CAD环境中设计规则应用一致性的方法和系统
公开(公告)号：US06915252B1
公开(公告)日：2005-07-05
申请号：US09481246
申请日：2000-01-11
申请人： Mu-Jing Li
发明人： Mu-Jing Li
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/50
摘要： In a computer-aided design environment, a method for ensuring consistency of design rule application among a plurality of CAD tool programs contemplates the use of a global design rule definition file containing one or more global variables each having a specific design rule characteristic assigned thereto. The values of the global variables are passed to CAD tool programs within the environment directly or indirectly through a technology file which contains a subset of the design rules. Each time a CAD tool session is initialized, the current set of design rules are updated through the use of the technology file and the global design rule definition file. Subsequent modifications or changes of the design rules requires only changing the global design rule definition file to ensure synchronization of design rule application among the various CAD tools in the environment.
摘要翻译：在计算机辅助设计环境中，用于确保多个CAD工具程序中的设计规则应用的一致性的方法考虑使用包含一个或多个全局变量的全局设计规则定义文件，每个变量具有分配给其的特定设计规则特征。全局变量的值通过包含设计规则子集的技术文件直接或间接传递到环境中的CAD工具程序。每次CAD工具会话初始化时，通过使用技术文件和全局设计规则定义文件来更新当前设计规则集。设计规则的后续修改或更改只需要更改全局设计规则定义文件，以确保环境中各种CAD工具之间的设计规则应用程序的同步。

9. 发明授权

US06883149B2 Via enclosure rule check in a multi-wide object class design layout 有权
标题翻译：通过机箱规则检查多宽度对象类设计布局
公开(公告)号：US06883149B2
公开(公告)日：2005-04-19
申请号：US10260811
申请日：2002-09-30
申请人： Mu-Jing Li , Amy Yang
发明人： Mu-Jing Li , Amy Yang
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： In a multi-wide class design layout, design rule checks for enclosure of multi wide class objects prevent false errors or false passes by performing such checks against the non-virtual boundaries of a wide class object, and not against the virtual boundaries. An exemplary embodiment provides a method for identifying as a violation, for each wide class wi object, any geometry on another layer which is located at least partially inside the wi object and has any portion thereof located within a distance encli of any non-virtual boundary of the wi object. The exemplary method is preferably performed using effective wide class objects.
摘要翻译：在多类别设计布局中，多宽类对象框架的设计规则检查通过对宽类对象的非虚拟边界执行此类检查，而不是针对虚拟边界来防止错误错误或错误传递。示例性实施例提供了一种用于为每个宽类别标识对象的至少部分地位于第n个对象内的另一层上的任何几何形状的冲突的方法并且其任何部分位于距离对象的任何非虚拟边界的距离范围内。优选地，使用有效的宽类对象来执行示例性方法。

10. 发明授权

US06832360B2 Pure fill via area extraction in a multi-wide object class design layout 有权
公开(公告)号：US06832360B2
公开(公告)日：2004-12-14
申请号：US10260816
申请日：2002-09-30
申请人： Mu-Jing Li
发明人： Mu-Jing Li
IPC分类号： G06F945
CPC分类号： G06F17/5081
摘要： In a multi-wide object class design layout, an automatic extraction of pure fill via areas (PFVA) among multi wide class objects treats the virtual boundaries of the wide objects differently than non-virtual boundaries to allow an extracted pure fill via area to extend across a virtual edge of a wide class object. An exemplary method is provided for deriving one or more pure fill via areas for geometries on a first layer in a design layout having multi-wide object classes on the first layer. The exemplary method includes forming a Current PFVA, initially as a PFVA for the geometries of the layer, and successively adjusting the Current PFVA for each higher wide object class corresponding to the geometries, to accommodate the respective enclosure rules for each higher wide object class.

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