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1. 发明授权

US08693259B2 Wordline-to-wordline stress configuration 有权
标题翻译：字线到字线应力配置
公开(公告)号：US08693259B2
公开(公告)日：2014-04-08
申请号：US13340437
申请日：2011-12-29
申请人： Mrinal Kochar , Jianmin Huang , Jun Wan , Jian Chen
发明人： Mrinal Kochar , Jianmin Huang , Jun Wan , Jian Chen
IPC分类号： G11C16/06
CPC分类号： G11C29/06 , G11C16/00 , G11C2029/1202
摘要： A method and system for performing wordline-to-wordline stress routines on a storage device is disclosed. Stress routines may be performed to reduce state widening in multi-level memory cells in the storage device. However, data retention problems may result if the stress routines are performed too often. In order to perform the stress routines at the proper times, a stress control variable is used. The stress control variable may be indicative of age of the storage device (such as the number of erase cycles performed on a memory block in the storage device). The stress control variable is input to a look-up table (or other logical construct), with the output of the look-up table indicating whether to perform the wordline-to-wordline stress routine. In this way, the stress routines may be performed to reduce state widening while reducing the ill effects of data retention.
摘要翻译：公开了一种用于在存储设备上执行字线到字线应力程序的方法和系统。可以执行应力程序以减少存储设备中的多级存储器单元中的状态变宽。但是，如果压力程序太频繁地执行，则可能会导致数据保留问题。为了在适当的时候执行压力程序，使用应力控制变量。应力控制变量可以指示存储设备的年龄（例如在存储设备中的存储器块上执行的擦除周期的数量）。压力控制变量被输入到查找表（或其他逻辑结构），查找表的输出指示是否执行字线到字线应力程序。以这种方式，可以执行应力程序以减少状态扩大，同时减少数据保留的不良影响。

2. 发明申请

US20130170301A1 Wordline-to-Wordline Stress Configuration 有权
标题翻译： Wordline到Wordline应力配置
公开(公告)号：US20130170301A1
公开(公告)日：2013-07-04
申请号：US13340437
申请日：2011-12-29
申请人： Mrinal Kochar , Jianmin Huang , Jun Wan , Jian Chen
发明人： Mrinal Kochar , Jianmin Huang , Jun Wan , Jian Chen
IPC分类号： G11C29/00
CPC分类号： G11C29/06 , G11C16/00 , G11C2029/1202
摘要： A method and system for performing wordline-to-wordline stress routines on a storage device is disclosed. Stress routines may be performed to reduce state widening in multi-level memory cells in the storage device. However, data retention problems may result if the stress routines are performed too often. In order to perform the stress routines at the proper times, a stress control variable is used. The stress control variable may be indicative of age of the storage device (such as the number of erase cycles performed on a memory block in the storage device). The stress control variable is input to a look-up table (or other logical construct), with the output of the look-up table indicating whether to perform the wordline-to-wordline stress routine. In this way, the stress routines may be performed to reduce state widening while reducing the ill effects of data retention.
摘要翻译：公开了一种用于在存储设备上执行字线到字线应力程序的方法和系统。可以执行应力程序以减少存储设备中的多级存储器单元中的状态变宽。但是，如果压力程序太频繁地执行，则可能会导致数据保留问题。为了在适当的时候执行压力程序，使用应力控制变量。应力控制变量可以指示存储设备的年龄（例如在存储设备中的存储器块上执行的擦除周期的数量）。压力控制变量被输入到查找表（或其他逻辑结构），查找表的输出指示是否执行字线到字线应力程序。以这种方式，可以执行应力程序以减少状态扩大，同时减少数据保留的不良影响。

3. 发明授权

US08379454B2 Detection of broken word-lines in memory arrays 有权
标题翻译：检测存储器阵列中断字符
公开(公告)号：US08379454B2
公开(公告)日：2013-02-19
申请号：US13101765
申请日：2011-05-05
申请人： Mrinal Kochar , Jianmin Huang , Jun Wan
发明人： Mrinal Kochar , Jianmin Huang , Jun Wan
IPC分类号： G11C16/04
CPC分类号： G11C29/52 , G11C16/3418 , G11C16/3459 , G11C29/025
摘要： Techniques and corresponding circuitry are presented for the detection of broken wordlines in a memory array. An “inter-word-line” comparison where the program loop counts of different word-lines are compared in order to determine whether a word-line may be defective. The number of programming pulses needed for the cells along a word-line WLn is compared to the number needed for a preceding word-line, such as WLn or WL(n−1), to see whether it exceeds this earlier value by a threshold value. If the word-line requires an excessive number of pulses, relative the earlier word-line, to complete programming, it is treated as defective.
摘要翻译：提供技术和相应的电路用于检测存储器阵列中的断字。比较不同字线的程序循环计数的字间对比比较，以确定字线是否有缺陷。将沿着字线WLn的单元所需的编程脉冲的数量与前一字线（例如WLn或WL（n-1））所需的数字进行比较，以查看其是否超过该较早的值一个阈值值。如果字线需要过多的脉冲数，相对于较早的字线，要完成编程，则将其视为有缺陷的。

4. 发明申请

US20120281479A1 Detection of Broken Word-Lines in Memory Arrays 有权
标题翻译：在内存数组中检测破碎的字线
公开(公告)号：US20120281479A1
公开(公告)日：2012-11-08
申请号：US13101765
申请日：2011-05-05
申请人： Mrinal Kochar , Jianmin Huang , Jun Wan
发明人： Mrinal Kochar , Jianmin Huang , Jun Wan
IPC分类号： G11C16/10
CPC分类号： G11C29/52 , G11C16/3418 , G11C16/3459 , G11C29/025
摘要： Techniques and corresponding circuitry are presented for the detection of broken wordlines in a memory array. One example considers an “inter-word-line” comparison where the program loop counts of different word-lines are compared in order to determine whether a word-line may be defective. For example, the number of programming pulses needed for the cells along a word-line WLn is compared to the number needed for a preceding word-line, such as WLn or WL(n−1), to see whether it exceeds this earlier value by a threshold value. If the word-line requires an excessive number of pulses, relative the earlier word-line, to complete programming, it is treated as defective.
摘要翻译：提供技术和相应的电路用于检测存储器阵列中的断字。一个例子考虑比较不同字线的程序循环计数以便确定字线是否有缺陷的字间对比比较。例如，将沿着字线WLn的单元所需的编程脉冲的数量与先前的字线（例如WLn或WL（n-1））所需的数字进行比较，以查看其是否超过该较早的值通过阈值。如果字线需要过多的脉冲数，相对于较早的字线，要完成编程，则将其视为有缺陷的。

5. 发明授权

US08473809B2 Data coding for improved ECC efficiency 有权
标题翻译：数据编码，提高ECC效率
公开(公告)号：US08473809B2
公开(公告)日：2013-06-25
申请号：US12839237
申请日：2010-07-19
申请人： Jun Wan , Alex Mak , Tien-Chien Kuo , Yan Li , Jian Chen
发明人： Jun Wan , Alex Mak , Tien-Chien Kuo , Yan Li , Jian Chen
IPC分类号： G06F11/00 , G11C29/00 , G11C7/00
CPC分类号： G11C11/5642 , G11C11/5628 , G11C29/00
摘要： Non-volatile storage devices and techniques for operating non-volatile storage are described herein. One embodiment includes accessing “n” pages of data to be programmed into a group of non-volatile storage elements. The “n” pages are mapped to a data state for each of the non-volatile storage elements based on a coding scheme that evenly distributes read errors across the “n” pages of data. Each of the non-volatile storage elements in the group are programmed to a threshold voltage range based on the data states to which the plurality of pages have been mapped. The programming may include programming the “n” pages simultaneously. In one embodiment, mapping the plurality of pages is based on a coding scheme that distributes a significant failure mode (for example, program disturb errors) to a first of the pages and a significant failure mode (for example, data retention errors) to a second of the pages.
摘要翻译：本文描述了用于操作非易失性存储器的非易失性存储设备和技术。一个实施例包括访问要编程到一组非易失性存储元件中的“n”页数据。基于在“n”页数据上均匀分布读取错误的编码方案，将“n”个页映射到每个非易失性存储元件的数据状态。基于已经映射了多个页面的数据状态，组中的每个非易失性存储元件被编程到阈值电压范围。编程可以包括同时对“n”页进行编程。在一个实施例中，映射多个页面是基于将显着的故障模式（例如，程序干扰错误）分配给第一页面的编码方案和将重大故障模式（例如，数据保留错误）分配给第二页。

6. 发明授权

US07616499B2 Retention margin program verification 有权
标题翻译：保留保证金计划验证
公开(公告)号：US07616499B2
公开(公告)日：2009-11-10
申请号：US11617541
申请日：2006-12-28
申请人： Jun Wan , Jeffrey W. Lutze , Jian Chen , Yan Li , Alex Mak
发明人： Jun Wan , Jeffrey W. Lutze , Jian Chen , Yan Li , Alex Mak
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/3454 , G11C16/3459 , G11C2211/5621
摘要： Data verification in a memory device using a portion of a data retention margin is provided. A bit count is read from the region to determine whether errors will result in the memory. A read in one or more retention margin portions is performed after the normal program verify sequence and if the number of bits in these regions is more than a pre-set the memory will fail verify status. A method of verifying data in a memory device includes the steps of: defining an retention margin between adjacent data thresholds; programming the memory device with data; determining whether bits are present in the data retention margin; and if the number of bits in the retention margin exceeds a threshold, generating an error.
摘要翻译：提供了使用部分数据保留余量的存储器件中的数据验证。从区域读取位计数，以确定错误是否会导致内存。在正常程序验证序列之后执行在一个或多个保留边缘部分中的读取，并且如果这些区域中的位数大于预设，则存储器将失败验证状态。验证存储器件中的数据的方法包括以下步骤：定义相邻数据阈值之间的保留余量; 使用数据对存储设备进行编程; 确定位是否存在于数据保留余量中; 并且如果保留余量中的比特数超过阈值，则产生错误。

7. 发明授权

US07463532B2 Comprehensive erase verification for non-volatile memory 有权
标题翻译：非易失性存储器的全面擦除验证
公开(公告)号：US07463532B2
公开(公告)日：2008-12-09
申请号：US11316119
申请日：2005-12-21
申请人： Dat Tran , Kiran Ponnuru , Jian Chen , Jeffrey W. Lutze , Jun Wan
发明人： Dat Tran , Kiran Ponnuru , Jian Chen , Jeffrey W. Lutze , Jun Wan
IPC分类号： G11C11/34
CPC分类号： G11C16/3468
摘要： Systems and methods in accordance with various embodiments can provide for comprehensive erase verification and defect detection in non-volatile semiconductor memory. In one embodiment, the results of erasing a group of storage elements is verified using a plurality of test conditions to better detect defective and/or insufficiently erased storage elements of the group. For example, the results of erasing a NAND string can be verified by testing charging of the string in a plurality of directions with the storage elements biased to turn on if in an erased state. If a string of storage elements passes a first test process or operation but fails a second test process or operation, the string can be determined to have failed the erase process and possibly be defective. By testing charging or conduction of the string in a plurality of directions, defects in any transistors of the string that are masked under one set of conditions may be exposed under a second set of bias conditions. For example, a string may pass an erase verification operation but then be read as including one or more programmed storage elements. Such a string can be defective and mapped out of the memory device.
摘要翻译：根据各种实施例的系统和方法可以提供非易失性半导体存储器中的全面擦除验证和缺陷检测。在一个实施例中，使用多个测试条件来验证擦除一组存储元件的结果，以更好地检测组中的有缺陷和/或不充分擦除的存储元件。例如，擦除NAND串的结果可以通过在多个方向上测试字符串的充电来验证，其中存储元件被偏置为在擦除状态下导通。如果一串存储元件通过第一个测试过程或操作，但是失败了第二个测试过程或操作，则可以确定该字符串已经失效了擦除过程并且可能是有缺陷的。通过在多个方向上测试串的充电或导通，在一组条件下被屏蔽的串的任何晶体管中的缺陷可能在第二组偏置条件下暴露。例如，字符串可以传递擦除验证操作，然后被读取为包括一个或多个编程的存储元件。这样的字符串可能是有缺陷的，并被映射出存储器件。

8. 发明授权

US07254071B2 Flash memory devices with trimmed analog voltages 有权
标题翻译：具有微调模拟电压的闪存设备
公开(公告)号：US07254071B2
公开(公告)日：2007-08-07
申请号：US11332567
申请日：2006-01-12
申请人： Loc Tu , Jeffrey Lutze , Jun Wan , Jian Chen
发明人： Loc Tu , Jeffrey Lutze , Jun Wan , Jian Chen
IPC分类号： G11C29/00
CPC分类号： G11C16/0483 , G11C7/16 , G11C11/5628 , G11C16/04 , G11C16/12 , G11C16/3454 , G11C16/3459 , G11C27/005 , G11C29/028 , G11C29/48 , G11C29/50 , G11C29/50004 , G11C2029/5004 , G11C2211/5621 , G11C2211/5634
摘要： A flash memory device of the multi-level cell (MLC) type, in which control gate voltages in read and programming operations and a bandgap reference voltage source are trimmable from external terminals, is disclosed. In a special test mode, control gate voltages can be applied to a selected programmed memory cell so that the threshold voltage of the cell can be sensed. A digital-to-analog converter (DAC) use for programming and a second read/verify DAC apply varying analog voltages and are sequentially used to verify the programming of an associated set of memory cells in this special test mode, with the DAC input values that provide the closest result selected for use in normal operation. These DAC's are dependent on the value of a reference source that my also be trimmed.
摘要翻译：公开了一种多电平单元（MLC）类型的闪速存储器件，其中读取和编程操作中的控制栅极电压和带隙基准电压源可从外部端子进行调节。在特殊测试模式中，可以将控制栅极电压施加到所选择的编程存储单元，从而可以感测单元的阈值电压。用于编程的数/模转换器（DAC）和第二读/验用DAC应用变化的模拟电压，并且在该特殊测试模式下依次用于验证相关联的存储器单元的编程，DAC输入值它提供了选择用于正常操作的最接近的结果。这些DAC取决于我也被修剪的参考源的值。

9. 发明授权

US07512014B2 Comprehensive erase verification for non-volatile memory 有权
标题翻译：非易失性存储器的全面擦除验证
公开(公告)号：US07512014B2
公开(公告)日：2009-03-31
申请号：US11316069
申请日：2005-12-21
申请人： Dat Tran , Kiran Ponnuru , Jian Chen , Jeffrey W. Lutze , Jun Wan
发明人： Dat Tran , Kiran Ponnuru , Jian Chen , Jeffrey W. Lutze , Jun Wan
IPC分类号： G11C11/34
CPC分类号： G11C16/3468
摘要： Systems and methods in accordance with various embodiments can provide for comprehensive erase verification and defect detection in non-volatile semiconductor memory. In one embodiment, the results of erasing a group of storage elements is verified using a plurality of test conditions to better detect defective and/or insufficiently erased storage elements of the group. For example, the results of erasing a NAND string can be verified by testing charging of the string in a plurality of directions with the storage elements biased to turn on if in an erased state. If a string of storage elements passes a first test process or operation but fails a second test process or operation, the string can be determined to have failed the erase process and possibly be defective. By testing charging or conduction of the string in a plurality of directions, defects in any transistors of the string that are masked under one set of conditions may be exposed under a second set of bias conditions. For example, a string may pass an erase verification operation but then be read as including one or more programmed storage elements. Such a string can be defective and mapped out of the memory device.
摘要翻译：根据各种实施例的系统和方法可以提供非易失性半导体存储器中的全面擦除验证和缺陷检测。在一个实施例中，使用多个测试条件来验证擦除一组存储元件的结果，以更好地检测组中的有缺陷和/或不充分擦除的存储元件。例如，擦除NAND串的结果可以通过在多个方向上测试字符串的充电来验证，其中存储元件被偏置为在擦除状态下导通。如果一串存储元件通过第一个测试过程或操作，但是失败了第二个测试过程或操作，则可以确定该字符串已经失效了擦除过程并且可能是有缺陷的。通过在多个方向上测试串的充电或导通，在一组条件下被屏蔽的串的任何晶体管中的缺陷可能在第二组偏置条件下暴露。例如，字符串可以传递擦除验证操作，然后被读取为包括一个或多个编程的存储元件。这样的字符串可能是有缺陷的，并被映射出存储器件。

10. 发明授权

US07508720B2 Systems for comprehensive erase verification in non-volatile memory 有权
标题翻译：非易失性存储器中的全面擦除验证系统
公开(公告)号：US07508720B2
公开(公告)日：2009-03-24
申请号：US11316475
申请日：2005-12-21
申请人： Dat Tran , Kiran Ponnuru , Jian Chen , Jeffrey W. Lutze , Jun Wan
发明人： Dat Tran , Kiran Ponnuru , Jian Chen , Jeffrey W. Lutze , Jun Wan
IPC分类号： G11C11/34
CPC分类号： G11C16/3468
摘要： Systems and methods in accordance with various embodiments can provide for comprehensive erase verification and defect detection in non-volatile semiconductor memory. In one embodiment, the results of erasing a group of storage elements is verified using a plurality of test conditions to better detect defective and/or insufficiently erased storage elements of the group. For example, the results of erasing a NAND string can be verified by testing charging of the string in a plurality of directions with the storage elements biased to turn on if in an erased state. If a string of storage elements passes a first test process or operation but fails a second test process or operation, the string can be determined to have failed the erase process and possibly be defective. By testing charging or conduction of the string in a plurality of directions, defects in any transistors of the string that are masked under one set of conditions may be exposed under a second set of bias conditions. For example, a string may pass an erase verification operation but then be read as including one or more programmed storage elements. Such a string can be defective and mapped out of the memory device.
摘要翻译：根据各种实施例的系统和方法可以提供非易失性半导体存储器中的全面擦除验证和缺陷检测。在一个实施例中，使用多个测试条件来验证擦除一组存储元件的结果，以更好地检测组中的有缺陷和/或不充分擦除的存储元件。例如，擦除NAND串的结果可以通过在多个方向上测试字符串的充电来验证，其中存储元件被偏置为在擦除状态下导通。如果一串存储元件通过第一个测试过程或操作，但是失败了第二个测试过程或操作，则可以确定该字符串已经失效了擦除过程并且可能是有缺陷的。通过在多个方向上测试串的充电或导通，在一组条件下被屏蔽的串的任何晶体管中的缺陷可能在第二组偏置条件下暴露。例如，字符串可以传递擦除验证操作，然后被读取为包括一个或多个编程的存储元件。这样的字符串可能是有缺陷的，并被映射出存储器件。

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