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1. 发明授权

US06291888B1 Contact structure and process for formation 失效
标题翻译：接触结构和形成过程
公开(公告)号：US06291888B1
公开(公告)日：2001-09-18
申请号：US09461251
申请日：1999-12-15
申请人： Mousumi Bhat , Mark D. Hall , Arkalgud R. Sitaram , Michael P. Woo
发明人： Mousumi Bhat , Mark D. Hall , Arkalgud R. Sitaram , Michael P. Woo
IPC分类号： H01L214763
CPC分类号： H01L21/76805 , H01L21/76831 , H01L21/76895
摘要： Electrical shorts and leakage paths are virtually eliminated by recessing conductive nodules (52) away from a conductor (72) or not forming the conductive nodules at all. In one embodiment, the refractory metal containing material (52) is recessed from the edge of the opening (32). When forming a nitride layer (54) within the opening (32), conductive nodules (52) are formed from a portion of the refractory metal containing material (20) such that the conductive nodules (52) lie within the recession (42). In another embodiment, an oxide layer (82, 102) is formed adjacent to the refractory metal containing material (20) before forming a nitride layer (84, 112).
摘要翻译：实际上通过使导电结节（52）远离导体（72）凹陷或完全不形成导电结节来消除电短路和漏电路径。在一个实施例中，含难熔金属材料（52）从开口（32）的边缘凹进。当在开口（32）内形成氮化物层（54）时，导电结核（52）由含难熔金属材料（20）的一部分形成，使得导电结核（52）位于凹陷（42）内。在另一个实施例中，在形成氮化物层（84,112）之前，邻近难熔金属材料（20）形成氧化物层（82,102）。

2. 发明授权

US06037246A Method of making a contact structure 失效
标题翻译：制作接触结构的方法
公开(公告)号：US06037246A
公开(公告)日：2000-03-14
申请号：US715303
申请日：1996-09-17
申请人： Mousumi Bhat , Mark D. Hall , Arkalgud R. Sitaram , Michael P. Woo
发明人： Mousumi Bhat , Mark D. Hall , Arkalgud R. Sitaram , Michael P. Woo
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/76805 , H01L21/76831 , H01L21/76895
摘要： Electrical shorts and leakage paths are virtually eliminated by recessing conductive nodules (52) away from a conductor (72) or not forming the conductive nodules at all. In one embodiment, the refractory metal containing material (52) is recessed from the edge of the opening (32). When forming a nitride layer (54) within the opening (32), conductive nodules (52) are formed from a portion of the refractory metal containing material (20) such that the conductive modules (52) lie within the recession (42). In another embodiment, an oxide layer (82, 102) is formed adjacent to the refractory metal containing material (20) before forming a nitride layer (84, 112).
摘要翻译：实际上通过使导电结节（52）远离导体（72）凹陷或完全不形成导电结节来消除电短路和漏电路径。在一个实施例中，含难熔金属材料（52）从开口（32）的边缘凹进。当在开口（32）内形成氮化物层（54）时，导电结核（52）由含难熔金属材料（20）的一部分形成，使得导电模块（52）位于凹陷（42）内。在另一个实施例中，在形成氮化物层（84,112）之前，邻近难熔金属材料（20）形成氧化物层（82,102）。

3. 发明授权

US5721167A Process for forming a semiconductor device and a static-random-access memory cell 失效
标题翻译：用于形成半导体器件和静态随机存取存储器单元的工艺
公开(公告)号：US5721167A
公开(公告)日：1998-02-24
申请号：US797142
申请日：1997-02-10
申请人： Chitra Subramanian , James D. Hayden , Olubunmi Adetutu , Dean Denning , Arkalgud R. Sitaram
发明人： Chitra Subramanian , James D. Hayden , Olubunmi Adetutu , Dean Denning , Arkalgud R. Sitaram
IPC分类号： H01L21/8244
CPC分类号： H01L27/11
摘要： A semiconductor device (10) is formed having an SRAM array with a plurality of SRAM cells. In forming the access and latch transistors, two different gate electrode compositions are used to form the access and latch transistors. More specifically, a dielectric layer (22) is formed between two conductive layers (26 and 28) within the gate electrode (52) for the access transistors while the dielectric layer is not formed between the two conductive layers (26 and 28) for the latch transistors. This structure allows an increase in the beta ratio for the SRAM cell thereby making a more stable SRAM cell without having to use diffused resistors between the access transistors in storage nodes or by having to form a differential thickness between the gate dielectric layers for the latch transistors and the access transistors.
摘要翻译：形成具有具有多个SRAM单元的SRAM阵列的半导体器件（10）。在形成访问和锁存晶体管时，使用两种不同的栅电极组合物来形成访问和锁存晶体管。更具体地，在用于存取晶体管的栅电极（52）内的两个导电层（26和28）之间形成介电层（22），而在两个导电层（26和28）之间不形成介电层，用于锁存晶体管。该结构允许增加SRAM单元的β比，从而形成更稳定的SRAM单元，而不必在存储节点中的存取晶体管之间使用扩散电阻，或者必须在用于锁存晶体管的栅介质层之间形成差分厚度和存取晶体管。

4. 发明授权

US5441914A Method of forming conductive interconnect structure 失效
标题翻译：形成导电互连结构的方法
公开(公告)号：US5441914A
公开(公告)日：1995-08-15
申请号：US236076
申请日：1994-05-02
申请人： Robert C. Taft , Craig D. Gunderson , Arkalgud R. Sitaram
发明人： Robert C. Taft , Craig D. Gunderson , Arkalgud R. Sitaram
IPC分类号： H01L21/027 , H01L21/28 , H01L21/3213 , H01L23/532 , H01L21/283 , H01L21/314
CPC分类号： H01L23/53271 , H01L21/0276 , H01L21/28061 , H01L21/28123 , H01L21/32137 , H01L21/32139 , H01L2924/0002 , Y10S148/012
摘要： In one embodiment, delamination of a patterned silicon nitride anti-reflective layer (26) from an underlying patterned tungsten silicide layer (32), is prevented by forming a thin silicon layer (30) between the patterned tungsten silicide layer (32) and the overlying patterned silicon nitride anti-reflective layer (26).
摘要翻译：在一个实施例中，通过在图案化硅化钨层（32）和图案化硅化钨层（32）之间形成薄硅层（30）来防止图案化的氮化硅抗反射层（26）从下面的图案化硅化钨层（32）覆盖图案化的氮化硅抗反射层（26）。

5. 发明授权

US5958508A Process for forming a semiconductor device 失效
标题翻译：用于形成半导体器件的工艺
公开(公告)号：US5958508A
公开(公告)日：1999-09-28
申请号：US828635
申请日：1997-03-31
申请人： Olubunmi Olufemi Adetutu , Dean J. Denning , James D. Hayden , Chitra K. Subramanian , Arkalgud R. Sitaram
发明人： Olubunmi Olufemi Adetutu , Dean J. Denning , James D. Hayden , Chitra K. Subramanian , Arkalgud R. Sitaram
IPC分类号： H01L29/43 , C23C16/44 , C23C16/455 , H01L21/02 , H01L21/205 , H01L21/28 , H01L21/768 , H01L21/8242 , H01L21/8244 , H01L21/8247 , H01L27/108 , H01L27/11 , H01L27/115 , H01L29/78 , H01L29/788 , H01L29/792 , C23C16/00 , H01L21/285
CPC分类号： C23C16/45523 , H01L21/76895 , H01L28/60
摘要： A metal-semiconductor layer (26) is formed over an insulating layer (20) such that the metal-semiconductor layer (26) is graded to have varying amounts of the semiconductor and metal throughout the layer. In one embodiment, the metal-semiconductor layer (26) has relatively higher silicon content near the layer's lower and upper surfaces. At the midpoint, the layer is close to stoichiometric tungsten silicide. In another embodiment, a metal-semiconductor-nitrogen layer is formed having nitrogen nearer the lower surface and essentially no nitrogen near the upper surface. The layer (26) can be formed using chemical vapor deposition or sputtering.
摘要翻译：金属半导体层（26）形成在绝缘层（20）上，使得金属半导体层（26）被分级以在整个层中具有不同量的半导体和金属。在一个实施例中，金属半导体层（26）在层的下表面和上表面附近具有相对较高的硅含量。在中点处，该层接近化学计量的硅化钨。在另一个实施方案中，形成具有更靠近下表面的氮并且在上表面附近基本上不含氮的金属 - 半导体 - 氮层。层（26）可以使用化学气相沉积或溅射形成。

6. 发明授权

US5352631A Method for forming a transistor having silicided regions 失效
标题翻译：用于形成具有硅化物区域的晶体管的方法
公开(公告)号：US5352631A
公开(公告)日：1994-10-04
申请号：US991801
申请日：1992-12-16
申请人： Arkalgud R. Sitaram , James R. Pfiester
发明人： Arkalgud R. Sitaram , James R. Pfiester
IPC分类号： H01L21/225 , H01L21/285 , H01L21/336 , H01L21/283
CPC分类号： H01L29/66507 , H01L21/28518 , H01L29/66575 , H01L29/6659 , H01L29/66628 , H01L21/2257 , H01L29/66545
摘要： A process for forming a transistor (10) begins by providing a substrate (12). Field oxide regions (14) or equivalent isolation is formed overlying or within the substrate (12). A gate oxide (16) and a conductive layer (18) are formed. A masking layer (20) is formed overlying the conductive layer (18). The masking layer (20) and the conductive layer (18) are etched to form a gate electrode and define a drain region (19) and a source region (21). Spacers (22) are formed adjacent the gate electrode. First silicided regions (26) are formed over the source and drain regions (21 and 19 respectively). The masking layer prevents the gate electrode from siliciding. The masking layer (20) is removed and a second silicided region (30) is formed overlying the gate electrode. The second silicided region (30) and the silicided regions (26) are made of different silicides.
摘要翻译：用于形成晶体管（10）的工艺通过提供衬底（12）开始。场氧化物区域（14）或等效隔离形成在衬底（12）之上或之内。形成栅极氧化物（16）和导电层（18）。形成覆盖导电层（18）的掩模层（20）。蚀刻掩模层（20）和导电层（18）以形成栅电极并限定漏区（19）和源极区（21）。隔板（22）形成在栅电极附近。在源极和漏极区（分别为21和19）上形成第一硅化区（26）。掩模层防止栅电极硅化。去除掩模层（20），并且形成覆盖栅电极的第二硅化区域（30）。第二硅化物区域（30）和硅化物区域（26）由不同的硅化物制成。

7. 发明授权

US5872385A Conductive interconnect structure and method of formation 失效
标题翻译：导电互连结构及形成方法
公开(公告)号：US5872385A
公开(公告)日：1999-02-16
申请号：US666722
申请日：1996-06-18
申请人： Robert C. Taft , Craig D. Gunderson , Arkalgud R. Sitaram
发明人： Robert C. Taft , Craig D. Gunderson , Arkalgud R. Sitaram
IPC分类号： H01L21/027 , H01L21/28 , H01L21/3213 , H01L23/532 , H01L31/0232
CPC分类号： H01L23/53271 , H01L21/0276 , H01L21/28061 , H01L21/28123 , H01L21/32137 , H01L21/32139 , H01L2924/0002 , Y10S148/012
摘要： In one embodiment, delamination of a patterned silicon nitride anti-reflective layer (26) from an underlying patterned tungsten silicide layer (32), is prevented by forming a thin silicon layer (30) between the patterned tungsten silicide layer (32) and the overlying patterned silicon nitride anti-reflective layer (26).
摘要翻译：在一个实施例中，通过在图案化硅化钨层（32）和图案化硅化钨层（32）之间形成薄硅层（30）来防止图案化的氮化硅抗反射层（26）从下面的图案化硅化钨层（32）覆盖图案化的氮化硅抗反射层（26）。

8. 发明授权

US5605865A Method for forming self-aligned silicide in a semiconductor device using vapor phase reaction 失效
标题翻译：在使用气相反应的半导体器件中形成自对准硅化物的方法
公开(公告)号：US5605865A
公开(公告)日：1997-02-25
申请号：US416124
申请日：1995-04-03
申请人： Papu D. Maniar , Arkalgud R. Sitaram
发明人： Papu D. Maniar , Arkalgud R. Sitaram
IPC分类号： H01L21/285
CPC分类号： H01L21/28518
摘要： Self-aligned silicide regions (24) are formed in a semiconductor device (10) using vapor phase reaction. A chemical vapor deposition system (40) is used, but rather than depositing a blanket silicide material, a precursor (48) is introduced into the reaction chamber (42) and reacts with only exposed silicon and polysilicon members of the device. The reaction is assisted by heating the substrate to a temperature at which the precursor is volatile. Because the precursor source reacts only with exposed silicon and polysilicon regions, subsequent etch steps are unnecessary. In one form, cobalt silicide regions are formed using a cobalt carbonyl as the precursor source.
摘要翻译：使用气相反应在半导体器件（10）中形成自对准硅化物区域（24）。使用化学气相沉积系统（40），而不是沉积覆盖层硅化物材料，前体（48）被引入反应室（42）中，并且仅与设备的暴露的硅和多晶硅构件反应。通过将基底加热到前体挥发性的温度来辅助反应。因为前体源仅与暴露的硅和多晶硅区域反应，所以后续的蚀刻步骤是不必要的。在一种形式中，使用羰基钴作为前体源形成钴硅化物区域。

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