专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5896317A Nonvolatile semiconductor memory device having data line dedicated to data loading 失效
标题翻译：具有专用于数据加载的数据线的非易失性半导体存储器件
公开(公告)号：US5896317A
公开(公告)日：1999-04-20
申请号：US852353
申请日：1997-05-07
申请人： Motoharu Ishii , Shinichi Kobayashi , Akinori Matsuo , Masashi Wada
发明人： Motoharu Ishii , Shinichi Kobayashi , Akinori Matsuo , Masashi Wada
IPC分类号： G11C17/00 , G11C16/02 , G11C16/10 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C7/00
CPC分类号： G11C16/10
摘要： It is assumed that, in each memory cell array, a first bit line corresponds to a selected address. In this case, a potential on only the first bit line attains H-level. Data to be loaded is supplied to a latch circuit corresponding to the first bit line through a data line arranged independently of the bit line. All the bit lines are reset upon every completion of loading of data of 1 byte. Therefore, rapid data reading can be performed even when data is to be read from a memory cell array immediately after the data is loaded into a latch circuit, or destruction of data already loaded into the latch circuit can be prevented. Further, a circuit area can be reduced.
摘要翻译：假定，每个存储器单元阵列中，第一位线对应于所选地址。在这种情况下，仅第一位线上的电位达到H电平。要加载的数据被提供给通过数据线对应于所述第一位线的锁存电路独立于位线的布置。每次完成1字节数据的加载后，所有位线都将被复位。因此，即使当数据要被从所述数据被装载之后立即进入锁存电路，或可以防止已经载入到锁存电路中的数据破坏的存储器单元阵列读取来执行快速的数据读取。此外，可以减少电路面积。

2. 发明授权

US5847995A Nonvolatile semiconductor memory device having a plurality of blocks provided on a plurality of electrically isolated wells 失效
标题翻译：具有设置在多个电隔离的井上的多个块的非易失性半导体存储器件
公开(公告)号：US5847995A
公开(公告)日：1998-12-08
申请号：US852354
申请日：1997-05-07
申请人： Shinichi Kobayashi , Shinji Kawai , Tadashi Omae , Makoto Oi , Akinori Matsuo , Masashi Wada , Kenji Kozakai
发明人： Shinichi Kobayashi , Shinji Kawai , Tadashi Omae , Makoto Oi , Akinori Matsuo , Masashi Wada , Kenji Kozakai
IPC分类号： G11C17/00 , G11C16/06 , G11C29/00 , G11C29/04 , G11C7/00
CPC分类号： G11C29/78
摘要： The inventive DINOR flash memory includes a plurality of blocks, a spare block and a spare word line block, which are formed on a plurality of electrically isolated P-type wells. When a word line-to-well short-circuit takes place in a certain block and another block is selected, the block causing the word line-to-well short-circuit is brought into a non-selected state. Thus, no leakage takes place in the block causing the word line-to-well short-circuit, to exert no bad influence on the selected block.
摘要翻译：本发明的DINOR闪速存储器包括形成在多个电隔离P型阱上的多个块，备用块和备用字线块。当在某个块中发生字线对阱短路并且选择另一个块时，导致字线对阱短路的块被带入非选择状态。因此，在导致字线到阱短路的块中不发生泄漏，对所选择的块不会产生不良影响。

3. 发明授权

US5852583A Semiconductor memory device that can realize high speed data read out 失效
标题翻译：可实现高速数据读出的半导体存储器件
公开(公告)号：US5852583A
公开(公告)日：1998-12-22
申请号：US848391
申请日：1997-05-08
申请人： Yasuhiko Taito , Shinji Kawai , Shinichi Kobayashi , Akinori Matsuo , Masashi Wada
发明人： Yasuhiko Taito , Shinji Kawai , Shinichi Kobayashi , Akinori Matsuo , Masashi Wada
IPC分类号： G11C17/00 , G11C8/08 , G11C16/06 , G11C8/00
CPC分类号： G11C8/08
摘要： Following latching of a word line select signal by a latch circuit, a transfer gate is turned off. When a word line is selected, the voltage applied to the latch circuit is shifted to a desired level to apply a desired voltage to the word line from a word line driver. As a result, a predecode signal is applied to a small size buffering circuit to be transmitted to the word line driver at a potential level between Vcc-GND. Therefore, the parasitic capacitance accompanying a predecode signal is reduced.
摘要翻译：在通过锁存电路锁存字线选择信号之后，转移门被关闭。当选择字线时，施加到锁存电路的电压被移动到期望的电平，以从字线驱动器向字线施加期望的电压。结果，将预解码信号施加到小尺寸缓冲电路，以在Vcc-GND之间的电位电平发送到字线驱动器。因此，伴随预解码信号的寄生电容减少。

4. 发明授权

US5257234A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US5257234A
公开(公告)日：1993-10-26
申请号：US842887
申请日：1992-02-26
申请人： Akinori Matsuo , Masashi Watanabe , Michio Fujimoto , Masashi Wada , Yoshiharu Nagayama , Kazuo Naito
发明人： Akinori Matsuo , Masashi Watanabe , Michio Fujimoto , Masashi Wada , Yoshiharu Nagayama , Kazuo Naito
IPC分类号： G11C8/00 , G11C8/10 , G11C13/00
CPC分类号： G11C8/10 , G11C8/00
摘要： Means for changing-over address signals is provided in an address input portion, and the order of the signals to be input to an address decoder is changed according to external control signals. Alternatively, a reading output circuit is provided which reads data in bit unit different from that of the writing input circuit. Thus, data can be read and written even when the number of bits of data differs between in case of accessing a built-in memory of an LSI inside the LSI and in case of accessing it from outside the LSI.
摘要翻译：在地址输入部分提供用于切换地址信号的装置，并且根据外部控制信号改变要输入到地址解码器的信号的顺序。或者，提供读取输出电路，其读取与写入输入电路不同的位单元的数据。因此，即使在访问LSI内的LSI的内置存储器和从LSI外部访问的情况下，即使数据的位数不同，也可以读取和写入数据。

5. 发明授权

US5105389A Semiconductor integrated circuit device 失效
公开(公告)号：US5105389A
公开(公告)日：1992-04-14
申请号：US621643
申请日：1990-12-04
申请人： Akinori Matsuo , Masashi Watanabe , Michio Fujimoto , Masashi Wada , Yoshiharu Nagayama , Kazuo Naito
发明人： Akinori Matsuo , Masashi Watanabe , Michio Fujimoto , Masashi Wada , Yoshiharu Nagayama , Kazuo Naito
IPC分类号： G11C8/00 , G11C8/10
CPC分类号： G11C8/10 , G11C8/00
摘要： Means for changing-over address signals is provided in an address input portion, and the order of the signals to be input to an address decoder is changed according to external control signals. Alternatively, a reading output circuit is provided which reads data in bit unit different from that of the writing input circuit. Thus, data can be read and written even when the number of bits of data differs between in case of accessing a built-in memory of an LSI inside the LSI and in case of accessing it from outside the LSI.

6. 发明授权

US5544098A Semiconductor memory device having an automatically activated verify function capability 失效
公开(公告)号：US5544098A
公开(公告)日：1996-08-06
申请号：US455152
申请日：1995-05-31
申请人： Akinori Matsuo , Masashi Watanabe , Masashi Wada , Takeshi Wada , Yasuhiro Nakamura
发明人： Akinori Matsuo , Masashi Watanabe , Masashi Wada , Takeshi Wada , Yasuhiro Nakamura
IPC分类号： G06F12/16 , G11C16/02 , G11C16/06 , G11C16/10 , G11C16/34 , G11C17/00 , G11C29/00 , G11C29/02 , G11C29/04 , G11C29/12 , G11C29/46 , G11C29/48 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C7/00
CPC分类号： G11C16/10 , G11C16/3454 , G11C16/3459 , G11C29/46 , G11C29/48
摘要： A semiconductor memory device having a plurality of nonvolatile memory devices or elements disposed in a matrix arrangement as one or more memory arrays is provided with a write operation and a verify mode which is automatically implemented when the write operation of the memory device ends. In connection with this, an auto-verify function is set in an internal circuit associated with the memory in accordance with a predetermined control signal and wherein a read mode subsequent to the write operation is implemented. During the auto-verify function, the read mode is implemented by effecting a data comparison circuit, such as an exclusive-OR logic circuit, which performs a coincidence/non-coincidence operation comparing the write data and the read data.

7. 发明授权

US5335204A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US5335204A
公开(公告)日：1994-08-02
申请号：US69988
申请日：1993-05-28
申请人： Akinori Matsuo , Masashi Watanabe , Michio Fujimoto , Masashi Wada , Yoshiharu Nagayama , Kazuo Naito
发明人： Akinori Matsuo , Masashi Watanabe , Michio Fujimoto , Masashi Wada , Yoshiharu Nagayama , Kazuo Naito
IPC分类号： G11C8/00 , G11C8/10 , G11C13/00
CPC分类号： G11C8/10 , G11C8/00
摘要： Means for changing-over address signals is provided in an address input portion, and the order of the signals to be input to an address decoder is changed according to external control signals. Alternatively, a reading output circuit is provided which reads data in bit unit different from that of the writing input circuit. Thus, data can be read and written even when the number of bits of data differs between in case of accessing a built-in memory of an LSI inside the LSI and in case of accessing it from outside the LSI.
摘要翻译：在地址输入部分提供用于切换地址信号的装置，并且根据外部控制信号改变要输入到地址解码器的信号的顺序。或者，提供读取输出电路，其读取与写入输入电路不同的位单元的数据。因此，即使在访问LSI内的LSI的内置存储器和从LSI外部访问的情况下，即使数据的位数不同，也可以读取和写入数据。

8. 发明授权

US5134583A Nonvolatile semiconductor memory device having redundant data lines and page mode programming 失效
标题翻译：具有冗余数据线和页面模式编程的非易失性半导体存储器件
公开(公告)号：US5134583A
公开(公告)日：1992-07-28
申请号：US440323
申请日：1989-11-22
申请人： Akinori Matsuo , Masashi Watanabe , Masashi Wada , Takeshi Wada , Yasuhiro Nakamura
发明人： Akinori Matsuo , Masashi Watanabe , Masashi Wada , Takeshi Wada , Yasuhiro Nakamura
IPC分类号： G11C16/02 , G11C16/06 , G11C17/00 , G11C29/00 , G11C29/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C29/78
摘要： A semiconductor memory device has a plurality of memory blocks, each block including a matrix arrangement of a plurality of nonvolatile memory elements. The device is also provided with at least one redundant data line which is selectively employed in place of a defective data line associated with a defective address in a memory block. The data lines corresponding to the respective memory blocks are selectively coupled to corresponding ones of first common data lines by a Y selector circuit in accordance with outputs of a first Y decoder, while a redundant data line is controllably coupled to a redundant common data line by a redundant selector circuit in accordance with an output of a redundant decoder. A plurality of data latch circuits are provided for transmitting therethrough write information data in accordance with outputs of a second Y decoder and a second redundant decoder, each one of the plurality of data latch circuits being paired with a respective one of a plurality of write amplifiers which transmit the write signals to the common data lines and redundant common data line. Therefore, of the plurality of data lines being addressed in the plurality of memory blocks, only a defective data line which corresponds to a defective address is replaced with a respective redundant data line.
摘要翻译：半导体存储器件具有多个存储块，每个块包括多个非易失性存储元件的矩阵排列。该设备还设置有至少一个冗余数据线，其被选择性地用于代替与存储器块中的缺陷地址相关联的有缺陷的数据线。对应于相应存储块的数据线根据第一Y解码器的输出由Y选择器电路选择性地耦合到相应的第一公用数据线，而冗余数据线可控地耦合到冗余公用数据线，根据冗余解码器的输出的冗余选择器电路。提供了多个数据锁存电路，用于根据第二Y解码器和第二冗余解码器的输出来传输写入信息数据，多个数据锁存电路中的每一个与多个写入放大器中的相应一个配对其将写信号发送到公共数据线和冗余公用数据线。因此，在多个存储块中寻址的多条数据线中，只有与缺陷地址对应的缺陷数据线被相应的冗余数据线替代。

9. 发明授权

US4989185A Semiconductor device with change-over circuit to access a memory area based upon internal or external signal 失效
标题翻译：具有转换电路的半导体器件，用于基于内部或外部信号访问存储器区域
公开(公告)号：US4989185A
公开(公告)日：1991-01-29
申请号：US219736
申请日：1988-07-15
申请人： Akinori Matsuo , Masashi Watanabe , Michio Fujimoto , Masashi Wada , Yoshiharu Nagayama , Kazuo Naito
发明人： Akinori Matsuo , Masashi Watanabe , Michio Fujimoto , Masashi Wada , Yoshiharu Nagayama , Kazuo Naito
IPC分类号： G11C8/00 , G11C8/10
CPC分类号： G11C8/10 , G11C8/00
摘要： A memory area within a semiconductor integrated circuit device is accessible through an address changeover circuit. External control signals instruct the memory device as to the addressing mode desired. Address signals originating externally are provided directly to the IC's address decoder circuits, while addresses originating internal to the IC are first shifted one or two bits to modify the address by a power of 2, then provided to the address decoder circuits. In this way, data of bit length N may be written to a memory array of bit length M, where M>N.

10. 发明授权

US5994732A Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US5994732A
公开(公告)日：1999-11-30
申请号：US852817
申请日：1997-05-07
申请人： Natsuo Ajika , Akinori Matsuo
发明人： Natsuo Ajika , Akinori Matsuo
IPC分类号： H01L21/8247 , G11C16/16 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/115 , G11C16/16
摘要： A nonvolatile semiconductor memory device has a plurality of p well regions in a memory cell array region. P well region is independently provided for each erase block. Each p well region is connected to a common well/source line driver, respectively. Well/source line driver is connected to a well/source power supply and a well/block decoder. Therefore, a nonvolatile semiconductor memory device which can inhibit a well disturbance in erase operation can be provided.
摘要翻译：非易失性半导体存储器件在存储单元阵列区域中具有多个p阱区域。独立地为每个擦除块提供P阱区。每个p阱区分别连接到公共阱/源极线驱动器。阱/源极线驱动器连接到阱/源电源和阱/块解码器。因此，可以提供可以抑制擦除操作中的良好干扰的非易失性半导体存储器件。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式