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    • 1. 发明申请
    • Multi-memory module circuit topology
    • 多内存模块电路拓扑
    • US20070257699A1
    • 2007-11-08
    • US11407814
    • 2006-04-20
    • Moises CasesDaniel De AraujoErdem MatogluPravin PatelNam Pham
    • Moises CasesDaniel De AraujoErdem MatogluPravin PatelNam Pham
    • H03K17/16
    • G11C5/04G11C5/063
    • A multi-memory module circuit topology is disclosed that includes a memory controller, a plurality of memory modules connected to the memory controller through a memory bus, and a resonator connected to the plurality of memory modules in a starburst topology. A method for reducing impedance discontinuities in a multi-memory module circuit is disclosed that includes providing a plurality of memory modules connected to a memory controller through a memory bus, selecting a starburst topology, and connecting a resonator to the plurality of memory module in dependence upon the selected starburst topology. An additional method for reducing impedance discontinuities in a multi-memory module circuit is disclosed that includes providing by a resonator a predetermined discontinuity reducing impedance at a predetermined location in the multi-memory module circuit between at least two memory modules, the multi-memory module circuit having a plurality of components of logically arranged around the predetermined location.
    • 公开了一种多存储器模块电路拓扑,其包括存储器控制器,通过存储器总线连接到存储器控制器的多个存储器模块,以及以星爆拓扑连接到多个存储器模块的谐振器。 公开了一种用于减少多存储器模块电路中的阻抗不连续性的方法,其包括通过存储器总线提供连接到存储器控制器的多个存储器模块,选择星爆拓扑,并且依次将谐振器连接到多个存储器模块 在选定的星爆拓扑上。 公开了一种用于减少多存储器模块电路中的阻抗不连续性的附加方法,其包括由谐振器在至少两个存储器模块之间的多存储器模块电路中的预定位置处提供预定的不连续性减小阻抗,所述多存储器模块 电路具有围绕预定位置逻辑布置的多个部件。