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1. 发明申请

US20060156215A1 Error type identification circuit for identifying different types of errors in communications devices 失效
标题翻译：用于识别通信设备中不同类型错误的错误类型识别电路
公开(公告)号：US20060156215A1
公开(公告)日：2006-07-13
申请号：US11033077
申请日：2005-01-11
申请人： Mohit Kapur , Jose Tierno
发明人： Mohit Kapur , Jose Tierno
IPC分类号： G06K5/00 , H03M13/00
CPC分类号： G06F11/26
摘要： An apparatus, method, and computer program product are disclosed for identifying types of errors that occur in a communications device under test and where only the presence of an error is indicated by an error checker. Each presence of an error bit in an error signal during a first period of time output from the error data checker is identified. The error bit indicates only that a mismatch occurred between an input signal input into the device and an output signal output from the device. The error bit is generated in response to an error in the device under test. The error bit includes no information about a type of the error. The type of the error is determined by determining a number of occurrences of the error bit in the error signal during the first period of time.
摘要翻译：公开了一种装置，方法和计算机程序产品，用于识别在被测通信设备中出现的错误类型，并且仅错误检查器指示错误的存在。识别在从错误数据检查器输出的第一时间周期内存在错误信号中的错误位的每一个。误差位仅指示输入到器件的输入信号与从器件输出的输出信号之间发生不匹配。响应于被测设备中的错误而产生错误位。错误位不包含有关错误类型的信息。误差的类型通过确定在第一时间段期间误差信号中出现的错误位数来确定。

2. 发明申请

US20070220184A1 Latency-locked loop (LLL) circuit, buffer including the circuit, and method of adjusting a data rate 审中-公开
标题翻译：延迟锁定环路（LLL）电路，包括电路的缓冲器以及调整数据速率的方法
公开(公告)号：US20070220184A1
公开(公告)日：2007-09-20
申请号：US11377177
申请日：2006-03-17
申请人： Jose Tierno
发明人： Jose Tierno
IPC分类号： G06F5/00
CPC分类号： G06F5/12
摘要： A latency locked loop (LLL) circuit for a first in first out (FIFO) buffer, includes a latency error estimator for estimating a latency error for the buffer by measuring a latency of the buffer and comparing the measured latency to a reference latency, a loop filter for converting the latency error into a computed data rate, and a data rate generator for adjusting a rate of data at least one of into and out of the buffer such that the rate of data matches the computed data rate.
摘要翻译：用于先进先出（FIFO）缓冲器的延迟锁定环路（LLL）电路包括延迟误差估计器，用于通过测量缓冲器的等待时间并将所测量的等待时间与参考等待时间进行比较来估计缓冲器的等待时间错误，循环滤波器，用于将延迟误差转换成计算数据速率;以及数据速率发生器，用于调整进入和离开缓冲器的数据的速率，使得数据速率与计算出的数据速率匹配。

3. 发明申请

US20060282745A1 Soft error protection in individual memory devices 失效
公开(公告)号：US20060282745A1
公开(公告)日：2006-12-14
申请号：US11140133
申请日：2005-05-27
申请人： Douglas Joseph , Mark Ritter , Jose Tierno
发明人： Douglas Joseph , Mark Ritter , Jose Tierno
IPC分类号： H03M13/00
CPC分类号： H03M13/03 , G06F11/1028 , G11C7/1006 , G11C2207/104
摘要： Techniques are disclosed for minimizing the effects of soft errors associated with memory devices that are individually accessible. By way of example, a method of organizing a column in a memory array of a memory device protected by an error correction code comprises the step of maximizing a distance of the error correction code by maximizing a physical distance between memory bits associated with a memory line within the column protected by the error correction code. Other soft error protection techniques may include use of a feed forward error correction code or use of a memory operation (e.g., read or write operation) suppress and retry approach.

4. 发明申请

US20070025483A1 Methods and apparatus for clock synchronization and data recovery in a receiver 有权
标题翻译：接收机中时钟同步和数据恢复的方法和装置
公开(公告)号：US20070025483A1
公开(公告)日：2007-02-01
申请号：US11193868
申请日：2005-07-29
申请人： Azita Emami-Neyestanak , Mounir Meghelli , Benjamin Parker , Sergey Rylov , Alexander Rylyakov , Jose Tierno
发明人： Azita Emami-Neyestanak , Mounir Meghelli , Benjamin Parker , Sergey Rylov , Alexander Rylyakov , Jose Tierno
IPC分类号： H04L7/00
CPC分类号： H04L7/0337
摘要： Clock synchronization and data recovery techniques are disclosed. For example, a technique for synchronizing a clock for use in recovering received data comprises the following steps/operations. A first clock (e.g., a data clock) is set for a first sampling cycle to a first phase position within a given unit interval in the received data. A second clock (e.g., a sweep clock) is swept through other phase positions with respect to the first phase position such that a transition from the given unit interval to another unit interval in the received data is determined. A sampling point is determined based on measurements at the phase positions associated with the second clock. The second clock is set to the phase position corresponding to the sampling point such that data may be recovered at that sampling point. Further, for a next sampling cycle, the first clock may be used to sweep through phase positions with respect to the set phase position of the second clock corresponding to the sampling point in the first sampling cycle such that a next sampling point may be determined.
摘要翻译：公开了时钟同步和数据恢复技术。例如，用于同步用于恢复接收到的数据的时钟的技术包括以下步骤/操作。将第一时钟（例如，数据时钟）设置为在接收到的数据中的给定单位间隔内的第一相位位置的第一采样周期。第二时钟（例如，扫频时钟）相对于第一相位位置被扫过其它相位位置，从而确定在接收数据中从给定单位间隔到另一个单位间隔的转变。基于与第二时钟相关联的相位位置处的测量来确定采样点。将第二时钟设置为对应于采样点的相位位置，使得可以在该采样点恢复数据。此外，对于下一采样周期，可以使用第一时钟相对于与第一采样周期中的采样点对应的第二时钟的设置相位位置扫描相位位置，使得可以确定下一采样点。

5. 发明申请

US20070139126A1 DIGITAL PHASE AND FREQUENCY DETECTOR 失效
标题翻译：数字相位和频率检测器
公开(公告)号：US20070139126A1
公开(公告)日：2007-06-21
申请号：US11610900
申请日：2006-12-14
申请人： Alexander Rylyakov , Jose Tierno
发明人： Alexander Rylyakov , Jose Tierno
IPC分类号： H03L7/00
CPC分类号： H03L7/091 , H03L7/093 , H03L2207/50
摘要： Disclosed are a digital phase-frequency detector and a method of operating a digital phase-frequency detector. The detector includes an input circuit, an output circuit and a reset circuit. In use, the input circuit receives first and second input signals during a plurality of cycles, and during a given one of the cycles, generates a first intermediate signal or a second intermediate signal depending on which of the first and second input signals was received first during that given one of said cycles. The output circuit receives these intermediate signals, and outputs, during said one cycle, a first output signal or a second output signal depending on which one of intermediate signals was received by the output circuit during said one cycle. The reset circuit applies a reset signal to the input circuit under defined conditions to begin a new one of said plurality of cycles.
摘要翻译：公开了一种数字相位频率检测器和操作数字相位频率检测器的方法。检测器包括输入电路，输出电路和复位电路。在使用中，输入电路在多个周期期间接收第一和第二输入信号，并且在给定的一个周期期间，根据第一和第二输入信号中的哪一个首先被接收来产生第一中间信号或第二中间信号在给定一个所述周期期间。输出电路接收这些中间信号，并且在所述一个周期期间输出第一输出信号或第二输出信号，取决于在所述一个周期期间由输出电路接收到哪个中间信号。复位电路在限定的条件下向输入电路施加复位信号以开始所述多个周期中的新的周期。

6. 发明申请

US20050074058A1 Methods and apparatus for snapshot-based equalization of a communications channel 失效
标题翻译：用于通信信道基于快照的均衡的方法和装置
公开(公告)号：US20050074058A1
公开(公告)日：2005-04-07
申请号：US10668562
申请日：2003-09-23
申请人： Jose Tierno
发明人： Jose Tierno
IPC分类号： H03H17/02 , H04L25/03 , H03H7/30
CPC分类号： H04L25/03038 , H03H17/0294 , H04L2025/03477 , H04L2025/03617
摘要： Equalization techniques for compensating distortion associated with a communications channel are provided. In one aspect of the invention, a method/apparatus for equalizing an input signal received from a communications channel includes the following steps/operations. At least one sampling is generated from the received input signal based on a clock signal unrelated to a clock signal used to recover data associated with the received input signal. Distortion associated with the communications channel is then compensated for based on at least a portion of the at least one generated sampling.
摘要翻译：提供了用于补偿与通信信道相关联的失真的均衡技术。在本发明的一个方面，一种用于均衡从通信信道接收的输入信号的方法/装置包括以下步骤/操作。基于与用于恢复与接收到的输入信号相关联的数据的时钟信号无关的时钟信号，从接收的输入信号产生至少一个采样。然后基于至少一个生成的采样的至少一部分来补偿与通信信道相关联的失真。

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