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    • 3. 发明授权
    • Method of fabricating a dual gate FET
    • 制造双栅极FET的方法
    • US07741182B2
    • 2010-06-22
    • US11815100
    • 2006-01-23
    • Wibo Daniel Van NoortFranciscus Petrus WiddershovenRadu Surdeanu
    • Wibo Daniel Van NoortFranciscus Petrus WiddershovenRadu Surdeanu
    • H01L21/336
    • H01L29/785H01L29/66795H01L29/7854
    • The invention provides a method of fabricating an extremely short-length dual-gate FET, using conventional semi-conductor processing techniques, with extremely small and reproducible fins with a pitch and a width that are both smaller than can be obtained with photolithographic techniques. On a protrusion (2) on a substrate (1), a first layer (3) and a second layer (4) are formed, after which the top surface of the protrusion (2) is exposed. A portion of the first layer (3) is selectively removed relative to the protrusion (2) and the second layer (4), thereby creating a fin (6) and a trench (5). Also a method is presented to form a plurality of fins (6) and trenches (5). The dual-gate FET is created by forming a gate electrode (7) in the trench(es) (5) and a source and drain region. Further a method is presented to fabricate an extremely short-length asymmetric dual-gate FET with two gate electrodes that can be biased separately.
    • 本发明提供了一种使用常规半导体处理技术制造极短的双栅极FET的方法,其具有非常小且可重现的鳍,其间距和宽度都小于可以用光刻技术获得的。 在基板(1)上的突起(2)上形成第一层(3)和第二层(4),然后露出突起(2)的上表面。 相对于突起(2)和第二层(4),第一层(3)的一部分被选择性地去除,从而形成翅片(6)和沟槽(5)。 还提出了形成多个翅片(6)和沟槽(5)的方法。 通过在沟槽(5)中形成栅电极(7)和源极和漏极区域来产生双栅极FET。 此外,提出了一种制造具有可分别偏置的两个栅电极的极短的非对称双栅极FET的方法。
    • 5. 发明授权
    • Circuit for providing a constant current
    • US06559711B2
    • 2003-05-06
    • US09902219
    • 2001-07-10
    • Franciscus Petrus WiddershovenAnne Johan Annema
    • Franciscus Petrus WiddershovenAnne Johan Annema
    • G05F110
    • G05F3/30
    • Two substantially identical currents (I1,a, I1,b) are subtracted from each other, while being generated by elements (10, 11) in such a way that noise in the current value of said two currents (I1,a, I1,b) is determined by shot noise. The differential current, determined only by shot noise, is supplied to a capacitor (13). A second current (I2) is used to charge a second capacitor (22, 29). It is periodically determined whether the value of a voltage across the first capacitor (13) is within or outside a range bounded by the (negative and positive values of the) voltage of the second capacitor (22, 29) which has been charged over the same period of time. The currents (I1,b, Ib) are set in dependence on the result of the comparison. The signal to set the currents (I1,b, Ib) also serves as control signal for an element (43) connected as a constant current source. The setting signal and thus the constant current (I0) delivered by the element (43) connected as a current source is to a high degree independent of the temperature sensitivity of different components of the circuit and is determined essentially solely by the ratio of values of similar components (10, 11, 20, 27, 43) of the circuit. By choosing components whose ratio appears in a value of the constant current (I0) delivered by the circuit and which have the same temperature dependence, it is achieved that the temperature dependence disappears completely or substantially completely from the constant current (I0) delivered by the circuit.
    • 9. 发明授权
    • One-time UV-programmable non-volatile semiconductor memory and method of programming such a semiconductor memory
    • 一次性UV可编程非易失性半导体存储器和编程这种半导体存储器的方法
    • US06437398B2
    • 2002-08-20
    • US09846599
    • 2001-04-30
    • Franciscus Petrus Widdershoven
    • Franciscus Petrus Widdershoven
    • H01L29788
    • H01L27/11521G11C16/18H01L27/115
    • One-time UV-programmable read-only memory (1) comprising a number of memory cells in the form of MOS transistors (T) which are arranged in a matrix of rows and columns, each transistor comprising a source and a drain zone (12) and a channel zone (13) formed in a surface zone (11) of a semiconductor substrate (10). Said semiconductor zones adjoin a surface (14) of the semiconductor substrate on which surface a layer structure (17) is formed comprising floating gates (16) and control gates (15). The layer structure is provided with windows (18) through which UV radiation can reach the edges of the floating gates. The memory is further provided with means for generating an electric voltage between the substrate (10) and the control gates (16) during programming the memory by means of UV radiation. Thus, the memory can be programmed without being externally contacted during programming.
    • 一次性UV可编程只读存储器(1)包括以行和列为矩阵排列的MOS晶体管(T)形式的多个存储器单元,每个晶体管包括源极和漏极区域(12) )和形成在半导体衬底(10)的表面区(11)中的沟道区(13)。 所述半导体区域邻接在半导体衬底的表面上形成有层结构(17)的表面(14),其包括浮动栅极(16)和控制栅极(15)。 层结构设置有窗口(18),UV辐射可以通过该窗口到达浮动门的边缘。 存储器还设置有用于在通过UV辐射对存储器进行编程期间在衬底(10)和控制栅极(16)之间产生电压的装置。 因此,可以在编程期间对存储器进行编程而不需要外部接触。