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1. 发明授权

US07923976B2 Fault protection circuit, method of operating a fault protection circuit and a voltage regulator employing the same 有权
标题翻译：故障保护电路，故障保护电路的运行方法及采用该故障保护电路的稳压器
公开(公告)号：US07923976B2
公开(公告)日：2011-04-12
申请号：US12329537
申请日：2008-12-05
申请人： Mohammad A. Al-Shyoukh , Eric C. Blackall
发明人： Mohammad A. Al-Shyoukh , Eric C. Blackall
IPC分类号： H02H7/12
CPC分类号： G05F1/569
摘要： Embodiments of the present disclosure provide a fault protection circuit, a method of operating a fault protection circuit and a voltage regulator. In one embodiment, the fault protection circuit is for use with the voltage regulator and includes an output power section having first and second MOS transistors configured to provide a regulated voltage on an output node of the voltage regulator. The fault protection circuit also includes a gate pull-down section connected to the first and second MOS transistors and configured to provide a gate pull-down MOS transistor to limit a current through the first and second MOS transistors during a current overload fault condition on the output node.
摘要翻译：本公开的实施例提供故障保护电路，操作故障保护电路和电压调节器的方法。在一个实施例中，故障保护电路用于电压调节器，并且包括输出功率部分，其具有被配置为在电压调节器的输出节点上提供调节电压的第一和第二MOS晶体管。故障保护电路还包括连接到第一和第二MOS晶体管的栅极下拉部分，并且被配置为提供栅极下拉MOS晶体管，以限制在电流过载故障状态下通过第一和第二MOS晶体管的电流输出节点。

2. 发明申请

US20090167266A1 FAULT PROTECTION CIRCUIT, METHOD OF OPERATING A FAULT PROTECTION CIRCUIT AND A VOLTAGE REGULATOR EMPLOYING THE SAME 有权
标题翻译：故障保护电路，故障保护电路的运行方法及使用其的电压稳压器
公开(公告)号：US20090167266A1
公开(公告)日：2009-07-02
申请号：US12329537
申请日：2008-12-05
申请人： Mohammad A. Al-Shyoukh , Eric C. Blackall
发明人： Mohammad A. Al-Shyoukh , Eric C. Blackall
IPC分类号： G05F1/569 , H02H9/02
CPC分类号： G05F1/569
摘要： Embodiments of the present disclosure provide a fault protection circuit, a method of operating a fault protection circuit and a voltage regulator. In one embodiment, the fault protection circuit is for use with the voltage regulator and includes an output power section having first and second MOS transistors configured to provide a regulated voltage on an output node of the voltage regulator. The fault protection circuit also includes a gate pull-down section connected to the first and second MOS transistors and configured to provide a gate pull-down MOS transistor to limit a current through the first and second MOS transistors during a current overload fault condition on the output node.
摘要翻译：本公开的实施例提供故障保护电路，操作故障保护电路和电压调节器的方法。在一个实施例中，故障保护电路用于电压调节器，并且包括输出功率部分，其具有被配置为在电压调节器的输出节点上提供调节电压的第一和第二MOS晶体管。故障保护电路还包括连接到第一和第二MOS晶体管的栅极下拉部分，并且被配置为提供栅极下拉MOS晶体管，以限制在电流过载故障状态下通过第一和第二MOS晶体管的电流输出节点。

3. 发明申请

US20080284391A1 FAULT PROTECTION CIRCUIT, METHOD OF OPERATING A FAULT PROTECTION CIRCUIT AND A VOLTAGE REGULATOR EMPLOYING THE SAME 审中-公开
标题翻译：故障保护电路，故障保护电路的运行方法及使用其的电压稳压器
公开(公告)号：US20080284391A1
公开(公告)日：2008-11-20
申请号：US11967506
申请日：2007-12-31
申请人： Mohammad A. Al-Shyoukh , Eric C. Blackall
发明人： Mohammad A. Al-Shyoukh , Eric C. Blackall
IPC分类号： G05F1/569
CPC分类号： G05F1/569
摘要： Embodiments of the present disclosure provide a fault protection circuit, a method of operating a fault protection circuit and a voltage regulator. In one embodiment, the fault protection circuit is for use with the voltage regulator and includes an output power section having first and second MOS transistors configured to provide a regulated voltage on an output node of the voltage regulator. The fault protection circuit also includes a gate pull-down section connected to the first and second MOS transistors and configured to provide a gate pull-down MOS transistor to limit a current through the first and second MOS transistors during a current overload fault condition on the output node.
摘要翻译：本公开的实施例提供故障保护电路，操作故障保护电路和电压调节器的方法。在一个实施例中，故障保护电路用于电压调节器，并且包括输出功率部分，其具有被配置为在电压调节器的输出节点上提供调节电压的第一和第二MOS晶体管。故障保护电路还包括连接到第一和第二MOS晶体管的栅极下拉部分，并且被配置为提供栅极下拉MOS晶体管，以限制在电流过载故障状态下通过第一和第二MOS晶体管的电流输出节点。

4. 发明申请

US20090115379A1 Soft-Start Circuit for Power Regulators 有权
标题翻译：功率调节器的软启动电路
公开(公告)号：US20090115379A1
公开(公告)日：2009-05-07
申请号：US11935734
申请日：2007-11-06
申请人： Mohammad A. Al-Shyoukh
发明人： Mohammad A. Al-Shyoukh
IPC分类号： G05F1/10 , G05F1/00
CPC分类号： G05F1/56 , Y10S323/901
摘要： One embodiment of the present invention includes a system for providing a soft-start for a power regulator comprising a differential transistor pair that receives an input current and conducts a first current through a first transistor and a second current through a second transistor. One of the first and second current changes in response to a change in the other to maintain a sum of the first and second current being substantially equal to the input current. The system also comprises a comparator that provides an output signal based on a comparison of a first input voltage and a second input voltage associated with the first current and the second current, respectively. The system further comprises a current source activated by the output signal to charge a capacitor that increases a soft-start reference voltage associated with control of the power regulator and which controls the change in the other of the first and second current.
摘要翻译：本发明的一个实施例包括一种用于为功率调节器提供软启动的系统，该系统包括接收输入电流并传导通过第一晶体管的第一电流和通过第二晶体管的第二电流的差分晶体管对。第一和第二电流中的一个响应于另一个的变化而保持第一和第二电流的总和大致等于输入电流。该系统还包括比较器，其基于分别与第一电流和第二电流相关联的第一输入电压和第二输入电压的比较来提供输出信号。该系统还包括由输出信号激活的电流源，以对电容器充电，该电容器增加与功率调节器的控制相关联的软启动参考电压，并且控制第一和第二电流中另一个的变化。

5. 发明授权

US07233275B2 Analog-to-digital converter with input signal range greater than supply voltage and extended dynamic range 有权
标题翻译：模数转换器，输入信号范围大于电源电压和扩展动态范围
公开(公告)号：US07233275B2
公开(公告)日：2007-06-19
申请号：US11280086
申请日：2005-11-16
申请人： Devrim Y. Aksin , Mohammad A. Al-Shyoukh
发明人： Devrim Y. Aksin , Mohammad A. Al-Shyoukh
IPC分类号： H03M1/34
CPC分类号： H03K17/063 , H03K3/356113 , H03M1/129 , H03M1/20
摘要： An analog-to-digital converter device capable of measuring inputs beyond a supply voltage including: an N bit analog-to-digital converter powered by a supply voltage and a reference voltage; a range resolution stage capable of receiving inputs at higher voltages than the supply voltage, providing an input to the analog-to-digital converter, and outputting a logic value of one for the N+1th bit in response to an input signal higher than the reference voltage; and a bootstrapped input multiplexer stage for connecting low voltage input signals directly to the analog-to-digital converter and for connecting input signals that can exceed the supply voltage to the range resolution stage.
摘要翻译：一种能够测量超过电源电压的输入的模拟 - 数字转换器装置，包括：由电源电压和参考电压供电的N位模数转换器; 范围分辨率级，其能够以比电源电压更高的电压接收输入，向模数转换器提供输入，并且响应于高于所述模数转换器的输入信号，输出针对第N + 1位的逻辑值1 参考电压; 以及用于将低电压输入信号直接连接到模拟 - 数字转换器并用于将可以超过电源电压的输入信号连接到范围分辨率级的自举输入多路复用器级。

6. 发明授权

US07176742B2 Bootstrapped switch with an input dynamic range greater than supply voltage 有权
标题翻译：自举开关，输入动态范围大于电源电压
公开(公告)号：US07176742B2
公开(公告)日：2007-02-13
申请号：US11168035
申请日：2005-06-27
申请人： Devrim Y. Aksin , Mohammad A. Al-Shyoukh
发明人： Devrim Y. Aksin , Mohammad A. Al-Shyoukh
IPC分类号： H03K17/16
CPC分类号： H03K17/063 , H03K3/356113 , H03M1/129 , H03M1/20
摘要： A bootstrapping circuit capable of sampling inputs beyond a supply voltage which includes a bootstrapped switch coupled between an input node and an output node, a first transistor having a first end coupled to a control node of the bootstrapped switch, a first capacitor having a first end coupled to a second end of the first transistor, a second transistor coupled between the first end of the first transistor and a supply node, and having a control node coupled to a first clock signal node, a third transistor coupled between the second end of the first transistor and the supply node, a charge pump having an output coupled to a control node of the third transistor, a level shifter having an output coupled to a second end of the first capacitor, a fourth transistor cross-coupled with, the first transistor, a fifth transistor having a second end coupled to the first end of the fourth transistor, and having a control node coupled to the output of the level shifter, and a sixth transistor coupled between the first end of the fifth transistor and a common node and having a control node coupled to the first clock signal node.
摘要翻译：一种自举电路，其能够对输入超过电源电压的输入进行采样，所述电源电压包括耦合在输入节点和输出节点之间的自举开关，第一晶体管具有耦合到所述自举开关的控制节点的第一端，第一电容器，耦合到第一晶体管的第二端，耦合在第一晶体管的第一端和电源节点之间并具有耦合到第一时钟信号节点的控制节点的第二晶体管，耦合在第一晶体管的第二端之间的第三晶体管，第一晶体管和供电节点，具有耦合到第三晶体管的控制节点的输出的电荷泵，具有耦合到第一电容器的第二端的输出的电平移位器，与第一晶体管交叉耦合的第四晶体管，第五晶体管，具有耦合到第四晶体管的第一端的第二端，并且具有耦合到电平移位器的输出的控制节点，以及第六晶体管耦合在第五晶体管的第一端和公共节点之间，并且具有耦合到第一时钟信号节点的控制节点。

7. 发明授权

US07843183B2 Real time clock (RTC) voltage regulator and method of regulating an RTC voltage 有权
标题翻译：实时时钟（RTC）电压调节器和调节RTC电压的方法
公开(公告)号：US07843183B2
公开(公告)日：2010-11-30
申请号：US11961945
申请日：2007-12-20
申请人： Mohammad A. Al-Shyoukh , Marcus M. Martins , Dircere Martins, legal representative
发明人： Mohammad A. Al-Shyoukh , Marcus M. Martins
IPC分类号： G05F1/40
CPC分类号： G05F1/56
摘要： A real time clock (RTC) voltage regulator, a method of regulating an RTC voltage and a power management integrated circuit (PMIC). In one embodiment, an RTC voltage regulator includes a current source configured to provide a first current and a voltage regulator having a common gate amplifier and a power device. The first current is employed to establish a reference voltage for the common gate amplifier and the common gate amplifier is configured to control the power device. The power device is configured to provide an RTC voltage for the common gate amplifier.
摘要翻译：实时时钟（RTC）稳压器，调节RTC电压的方法和电源管理集成电路（PMIC）。在一个实施例中，RTC电压调节器包括被配置为提供具有公共栅极放大器和功率器件的第一电流和电压调节器的电流源。采用第一电流来建立公共栅极放大器的参考电压，公共栅极放大器被配置为控制功率器件。功率器件被配置为为公共栅极放大器提供RTC电压。

8. 发明申请

US20100117682A1 Level-Shifter Circuit 有权
标题翻译：电平移位电路
公开(公告)号：US20100117682A1
公开(公告)日：2010-05-13
申请号：US12346200
申请日：2008-12-30
申请人： Mohammad A. Al-Shyoukh , Ayman A. Fayed
发明人： Mohammad A. Al-Shyoukh , Ayman A. Fayed
IPC分类号： H03K19/0175 , H03L5/00
CPC分类号： H03K3/35613
摘要： One embodiment of the invention includes a level-shifter circuit. The circuit comprises a control stage that steers a current from one of a first control node and a second control node to the other of the first control node and the second control node based on an input signal to set a first initial voltage at the first control node and a second initial voltage at the second control node, the input signal having logic-high and logic-low voltage magnitudes that occupy a low voltage domain. The circuit also includes a logic driver that is coupled to the second control node and is referenced in a high voltage domain. The logic driver can be configured to provide an output signal having logic-high and logic-low voltage magnitudes that occupy the high voltage domain based on the second initial voltage.
摘要翻译：本发明的一个实施例包括电平移位器电路。该电路包括控制级，该控制级基于输入信号将电流从第一控制节点和第二控制节点之一引导到第一控制节点和第二控制节点中的另一个，以在第一控制下设置第一初始电压节点和第二控制节点处的第二初始电压，所述输入信号具有占用低电压域的逻辑高和逻辑低电压幅度。电路还包括耦合到第二控制节点的逻辑驱动器，并在高电压域中被参考。逻辑驱动器可以被配置为提供具有基于第二初始电压占据高电压域的逻辑高和逻辑低电压幅度的输出信号。

9. 发明申请

US20070216383A1 SOFT-START CIRCUIT AND METHOD FOR LOW-DROPOUT VOLTAGE REGULATORS 有权
标题翻译：软启动电路和低压差稳压器的方法
公开(公告)号：US20070216383A1
公开(公告)日：2007-09-20
申请号：US11683074
申请日：2007-03-07
申请人： Mohammad A. Al-Shyoukh , Marcus M. Martins , Devrim Yilmaz Aksin
发明人： Mohammad A. Al-Shyoukh , Marcus M. Martins , Devrim Yilmaz Aksin
IPC分类号： G05F1/00
CPC分类号： G05F1/468 , Y10S323/901 , Y10S323/908
摘要： A low drop-out voltage regulator having soft-start. A low drop-out regulator circuit is provided having an input node, an output node, a power FET connected by a source and drain between the input node and the output node, and a feedback circuit having an output connected and providing a control signal to a gate of the power FET. A current limit circuit is configured to control the power FET to limit the current through it when the voltage across a controllable sense resistor connected to conduct a current representing the current through the power FET exceeds a predetermined limit value. At start-up, control unit provides a control signal to the controllable resistor to cause the resistance value of the controllable resistor to decrease incrementally in value at respective predetermined incremental times during a predetermined time interval.
摘要翻译：具有软启动的低压差稳压器。提供一种具有输入节点，输出节点，通过输入节点和输出节点之间的源极和漏极连接的功率FET的低压差稳压器电路，以及反馈电路，其具有连接的输出并提供控制信号功率FET的栅极。电流限制电路被配置为当连接到可控感测电阻器两端的电压以传导表示通过功率FET的电流的电流超过预定极限值时，控制功率FET来限制通过其的电流。在启动时，控制单元向可控电阻提供控制信号，以使得可控电阻器的电阻值在预定的时间间隔内在各自的预定增量时间内递减地减小。

10. 发明授权

US07199621B1 Low AC impedance input stage for fast startup applications 有权
标题翻译：用于快速启动应用的低交流阻抗输入级
公开(公告)号：US07199621B1
公开(公告)日：2007-04-03
申请号：US11324645
申请日：2006-01-03
申请人： Mohammad A. Al-Shyoukh , Raul A. Perez
发明人： Mohammad A. Al-Shyoukh , Raul A. Perez
IPC分类号： H03K5/22
CPC分类号： H03K5/2481 , H03F1/56 , H03F3/45179 , H03F2200/222 , H03F2203/45306 , H03F2203/45326 , H03F2203/45342 , H03F2203/45352
摘要： The low AC impedance input stage circuit for fast startup applications includes: a first transistor coupled between a first input node and a first output node; a second transistor coupled between a second input node and a second output node, and having a control node coupled to a control node of the first transistor; a third transistor coupled to the first input node and having a control node coupled to the control node of the first transistor; a fourth transistor coupled to the second input node and having a control node coupled to the control node of the third transistor; a first blocking device coupled between the third transistor and a first current source; a second blocking device coupled between the fourth transistor and the first current source; and a bias device coupled between the first current source and the control node of the first transistor.
摘要翻译：用于快速启动应用的低AC阻抗输入级电路包括：耦合在第一输入节点和第一输出节点之间的第一晶体管; 第二晶体管，耦合在第二输入节点和第二输出节点之间，并且具有耦合到所述第一晶体管的控制节点的控制节点; 耦合到第一输入节点并且具有耦合到第一晶体管的控制节点的控制节点的第三晶体管; 耦合到第二输入节点并且具有耦合到第三晶体管的控制节点的控制节点的第四晶体管; 耦合在所述第三晶体管和第一电流源之间的第一阻断装置; 耦合在所述第四晶体管和所述第一电流源之间的第二阻断装置; 以及耦合在所述第一晶体管的所述第一电流源和所述控制节点之间的偏置装置。

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