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    • 1. 发明申请
    • SOFT-START CIRCUIT AND METHOD FOR LOW-DROPOUT VOLTAGE REGULATORS
    • 软启动电路和低压差稳压器的方法
    • US20070216383A1
    • 2007-09-20
    • US11683074
    • 2007-03-07
    • Mohammad A. Al-ShyoukhMarcus M. MartinsDevrim Yilmaz Aksin
    • Mohammad A. Al-ShyoukhMarcus M. MartinsDevrim Yilmaz Aksin
    • G05F1/00
    • G05F1/468Y10S323/901Y10S323/908
    • A low drop-out voltage regulator having soft-start. A low drop-out regulator circuit is provided having an input node, an output node, a power FET connected by a source and drain between the input node and the output node, and a feedback circuit having an output connected and providing a control signal to a gate of the power FET. A current limit circuit is configured to control the power FET to limit the current through it when the voltage across a controllable sense resistor connected to conduct a current representing the current through the power FET exceeds a predetermined limit value. At start-up, control unit provides a control signal to the controllable resistor to cause the resistance value of the controllable resistor to decrease incrementally in value at respective predetermined incremental times during a predetermined time interval.
    • 具有软启动的低压差稳压器。 提供一种具有输入节点,输出节点,通过输入节点和输出节点之间的源极和漏极连接的功率FET的低压差稳压器电路,以及反馈电路,其具有连接的输出并提供控制信号 功率FET的栅极。 电流限制电路被配置为当连接到可控感测电阻器两端的电压以传导表示通过功率FET的电流的电流超过预定极限值时,控制功率FET来限制通过其的电流。 在启动时,控制单元向可控电阻提供控制信号,以使得可控电阻器的电阻值在预定的时间间隔内在各自的预定增量时间内递减地减小。
    • 2. 发明授权
    • Soft-start circuit and method for low-dropout voltage regulators
    • 软启动电路和低压差稳压器的方法
    • US07459891B2
    • 2008-12-02
    • US11683074
    • 2007-03-07
    • Mohammad A. Al-ShyoukhMarcus M MartinsDevrim Yilmaz Aksin
    • Mohammad A. Al-ShyoukhMarcus M MartinsDevrim Yilmaz Aksin
    • G05F1/565G05F1/575
    • G05F1/468Y10S323/901Y10S323/908
    • A low drop-out voltage regulator having soft-start. A low drop-out regulator circuit is provided having an input node, an output node, a power FET connected by a source and drain between the input node and the output node, and a feedback circuit having an output connected and providing a control signal to a gate of the power FET. A current limit circuit is configured to control the power FET to limit the current through it when the voltage across a controllable sense resistor connected to conduct a current representing the current through the power FET exceeds a predetermined limit value. At start-up, control unit provides a control signal to the controllable resistor to cause the resistance value of the controllable resistor to decrease incrementally in value at respective predetermined incremental times during a predetermined time interval.
    • 具有软启动的低压差稳压器。 提供一种具有输入节点,输出节点,通过输入节点和输出节点之间的源极和漏极连接的功率FET的低压差稳压器电路,以及反馈电路,其具有连接的输出并提供控制信号 功率FET的栅极。 电流限制电路被配置为当连接到可控感测电阻器两端的电压以传导表示通过功率FET的电流的电流超过预定极限值时,控制功率FET来限制通过其的电流。 在启动时,控制单元向可控电阻提供控制信号,以使得可控电阻器的电阻值在预定的时间间隔内在各自的预定增量时间内递减地减小。