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1. 发明授权

US08327204B2 High-speed transceiver tester incorporating jitter injection 失效
标题翻译：采用抖动注入的高速收发器测试仪
公开(公告)号：US08327204B2
公开(公告)日：2012-12-04
申请号：US11553035
申请日：2006-10-26
申请人： Mohamed M. Hafed , Sebastien Laberge , Bardia Pishdad , Clarence K. L. Tam
发明人： Mohamed M. Hafed , Sebastien Laberge , Bardia Pishdad , Clarence K. L. Tam
IPC分类号： G01R31/3183 , G01R31/40
CPC分类号： G01R31/31709 , H04B17/15 , H04B17/20
摘要： A tester for testing high-speed serial transceiver circuitry. The tester includes a jitter generator that uses a rapidly varying phase-selecting signal to select between two or more differently phased clock signals to generate a phase-modulated signal. The phase-selecting signal is designed to contain low- and high-frequency components. The phase-modulated signal is input into a phase filter to filter unwanted high-frequency components. The filtered output of the phase filter is input into a data-transmit serializer to serialize a low-speed parallel word into a high-speed jittered test pattern for input into the transceiver circuitry.
摘要翻译：用于测试高速串行收发器电路的测试仪。该测试器包括抖动发生器，其使用快速变化的相位选择信号在两个或更多个不同相位的时钟信号之间进行选择以产生相位调制信号。相位选择信号被设计成包含低频和高频分量。相位调制信号被输入到相位滤波器中以滤除不需要的高频分量。相位滤波器的滤波输出被输入到数据发送串行器中以串行化低速并行字到高速抖动测试图案中，以便输入到收发器电路。

2. 发明授权

US07242209B2 System and method for testing integrated circuits 失效
标题翻译：集成电路测试系统和方法
公开(公告)号：US07242209B2
公开(公告)日：2007-07-10
申请号：US10838846
申请日：2004-05-03
申请人： Gordon W. Roberts , Antonio H. Chan , Geoffrey D. Duerden , Mohamed M. Hafed , Sébastien Laberge , Bardia Pishdad , Clarence K. L. Tam
发明人： Gordon W. Roberts , Antonio H. Chan , Geoffrey D. Duerden , Mohamed M. Hafed , Sébastien Laberge , Bardia Pishdad , Clarence K. L. Tam
IPC分类号： G01R31/26
CPC分类号： G01R31/31907 , G01R31/319 , G01R31/31928
摘要： A module (236, 236′) containing an integrated testing system (108) that includes one or more measurement engines (200, 202) tightly coupled with a compute engine (208). The one or more measurement engines include at least one stimulus instrument (212) for exciting circuitry of a device-under-test (104) with one or more stimulus signals, and at least one measurement instrument (216) that measures the response of the device-under-test to the stimulus signal(s) and generates measurement data. The compute engine includes computation logic circuitry (800) for determining whether or not the circuitry aboard the device-under-test passes or fails. The integrated testing system further includes a communications engine (204) providing two-way communications between the integrated testing system automated testing equipment (116) and/or a dedicated user interface (140) residing on a host computer (136).
摘要翻译：包括集成测试系统（108）的模块（236,236'），其包括与计算引擎（208）紧密耦合的一个或多个测量引擎（200,202）。一个或多个测量引擎包括至少一个激励仪器（212），用于激励具有一个或多个激励信号的被测设备（104）的电路，以及至少一个测量仪器（216）刺激信号下测试装置，并产生测量数据。计算引擎包括计算逻辑电路（800），用于确定被测设备中的电路是否通过或失败。集成测试系统还包括在集成测试系统自动测试设备（116）和/或驻留在主计算机（136）上的专用用户界面（140）之间提供双向通信的通信引擎（204）。

3. 发明申请

US20080192814A1 System and Method for Physical-Layer Testing of High-Speed Serial Links in their Mission Environments 审中-公开
标题翻译：其任务环境中高速串行链路物理层测试的系统和方法
公开(公告)号：US20080192814A1
公开(公告)日：2008-08-14
申请号：US12028577
申请日：2008-02-08
申请人： Mohamed M. Hafed , Donald Dansereau , Geoffrey Duerden , Sebastien Laberge , Yvon Nazon , Clarence Kar Lun Tam
发明人： Mohamed M. Hafed , Donald Dansereau , Geoffrey Duerden , Sebastien Laberge , Yvon Nazon , Clarence Kar Lun Tam
IPC分类号： H04B3/46
CPC分类号： G01R31/31711 , G01R31/31901 , H04L43/50
摘要： A physical-layer tester for testing a high-speed serial link between a mission-environment transmitter and a mission-environment receiver. The tester includes a data path and a measurement path. The data path allows a data signal transmitted from the mission-environment transmitter to be passed through the tester to the mission-environment receiver. The measurement path includes circuitry for use in analyzing characteristics of the high-speed serial data traffic on the high-speed serial link. The tester is placed in the high-speed serial link and allows the link to be tested while live, mission-environment data is present on the link. Methods for implementing in-link testing are also disclosed.
摘要翻译：用于测试任务环境发射机和任务环境接收机之间的高速串行链路的物理层测试仪。测试仪包括数据路径和测量路径。数据路径允许从任务环境发射机发送的数据信号通过测试仪传递到任务环境接收器。测量路径包括用于分析高速串行数据业务在高速串行链路上的特性的电路。测试仪放置在高速串行链路中，并允许测试链路，同时实时，任务环境数据存在于链路上。还公开了实现链路测试的方法。

4. 发明申请

US20080048726A1 Signal Integrity Measurement Systems and Methods Using a Predominantly Digital Time-Base Generator 失效
标题翻译：使用主要数字时基发生器的信号完整性测量系统和方法
公开(公告)号：US20080048726A1
公开(公告)日：2008-02-28
申请号：US11776825
申请日：2007-07-12
申请人： Mohamed M. Hafed
发明人： Mohamed M. Hafed
IPC分类号： G01R29/26 , G01R25/00 , G06F15/04 , H03K17/18 , H03K7/00
CPC分类号： G01R31/2882 , G01R31/31709 , G01R31/31725 , G01R31/31727
摘要： Signal-integrity measurement systems and methods utilizing unique time-base generation techniques for controlling the sampling of one or more signals under test. A time-base generator made in accordance with the present disclosure includes a phase filter and modulation circuitry that generates a rapidly varying phase signal as a function of the output of a sigma-delta modulator. The phase filter filters unwanted high-frequency phase components from the rapidly varying phase signal. The filtered signal is used to clock one or more samplers so as to create sampling instances of the signal(s) under test. The sampling instances are then analyze using any one or more of a variety of techniques suited to the type of signal(s) under test.
摘要翻译：信号完整性测量系统和方法利用独特的时基生成技术来控制一个或多个待测信号的采样。根据本公开制造的时基发生器包括相位滤波器和调制电路，其产生作为Σ-Δ调制器的输出的函数的快速变化的相位信号。相位滤波器从快速变化的相位信号滤除不想要的高频相位分量。经过滤波的信号用于对一个或多个采样器进行定时，以创建被测信号的采样实例。然后使用适合于被测信号类型的各种技术中的任何一种或多种来分析采样实例。

5. 发明授权

US08244492B2 Methods of parametric testing in digital circuits 失效
标题翻译：数字电路参数测试方法
公开(公告)号：US08244492B2
公开(公告)日：2012-08-14
申请号：US13044309
申请日：2011-03-09
申请人： Mohamed M. Hafed
发明人： Mohamed M. Hafed
IPC分类号： G01R31/26 , G06F11/26
CPC分类号： G01R31/31858
摘要： Delay-fault testing and parametric analysis systems and methods utilizing one or more variable delay time-base generators. In embodiments of the delay-fault testing systems, short-delay logic paths are provided with additional scan-chain memory elements and logic that, in conjunction with the one or more variable-delay time-base generators, provides the effect of over-clocking without the need to over-clock. Related methods provide such effective over-clocking. In embodiments of parametric analysis systems, test point sampling elements and analysis circuitry are clocked as a function of the output of the one or more variable-delay time-base generators to provide various parametric analysis functionality. Related methods address this functionality.
摘要翻译：使用一个或多个可变延迟时基发生器的延迟故障测试和参数分析系统和方法。在延迟故障测试系统的实施例中，短延迟逻辑路径被提供有额外的扫描链存储器元件和逻辑，其结合一个或多个可变延迟时基发生器提供超频时钟效应而不需要超时钟。相关方法提供了这种有效的超频。在参数分析系统的实施例中，测试点采样元件和分析电路作为一个或多个可变延迟时基发生器的输出的函数被计时以提供各种参数分析功能。相关方法解决了这个功能。

6. 发明授权

US07681091B2 Signal integrity measurement systems and methods using a predominantly digital time-base generator 失效
标题翻译：信号完整性测量系统和使用主要数字时基发生器的方法
公开(公告)号：US07681091B2
公开(公告)日：2010-03-16
申请号：US11776825
申请日：2007-07-12
申请人： Mohamed M. Hafed
发明人： Mohamed M. Hafed
IPC分类号： G06K5/04 , G06K5/00 , G06F11/00
CPC分类号： G01R31/2882 , G01R31/31709 , G01R31/31725 , G01R31/31727
摘要： Signal-integrity measurement systems and methods utilizing unique time-base generation techniques for controlling the sampling of one or more signals under test. A time-base generator made in accordance with the present disclosure includes a phase filter and modulation circuitry that generates a rapidly varying phase signal as a function of the output of a sigma-delta modulator. The phase filter filters unwanted high-frequency phase components from the rapidly varying phase signal. The filtered signal is used to clock one or more samplers so as to create sampling instances of the signal(s) under test. The sampling instances are then analyze using any one or more of a variety of techniques suited to the type of signal(s) under test.
摘要翻译：信号完整性测量系统和方法利用独特的时基生成技术来控制一个或多个待测信号的采样。根据本公开制造的时基发生器包括相位滤波器和调制电路，其产生作为Σ-Δ调制器的输出的函数的快速变化的相位信号。相位滤波器从快速变化的相位信号滤除不想要的高频相位分量。经过滤波的信号用于对一个或多个采样器进行定时，以创建被测信号的采样实例。然后使用适合所测试信号类型的各种技术中的任何一种或多种来分析采样实例。

7. 发明申请

US20090198461A1 Systems and Methods for Testing and Diagnosing Delay Faults and For Parametric Testing in Digital Circuits 有权
标题翻译：用于测试和诊断数字电路中延迟故障和参数测试的系统和方法
公开(公告)号：US20090198461A1
公开(公告)日：2009-08-06
申请号：US12026760
申请日：2008-02-06
申请人： Mohamed M. Hafed
发明人： Mohamed M. Hafed
IPC分类号： G01R29/26 , G06F11/00 , G06F19/00
CPC分类号： G01R31/31858
摘要： Delay-fault testing and parametric analysis systems and methods utilizing one or more variable delay time-base generators. In embodiments of the delay-fault testing systems, short-delay logic paths are provided with additional scan-chain memory elements and logic that, in conjunction with the one or more variable-delay time-base generators, provides the effect of over-clocking without the need to over-clock. Related methods provide such effective over-clocking. In embodiments of parametric analysis systems, test point sampling elements and analysis circuitry are clocked as a function of the output of the one or more variable-delay time-base generators to provide various parametric analysis functionality. Related methods address this functionality.
摘要翻译：使用一个或多个可变延迟时基发生器的延迟故障测试和参数分析系统和方法。在延迟故障测试系统的实施例中，短延迟逻辑路径被提供有额外的扫描链存储器元件和逻辑，其结合一个或多个可变延迟时基发生器提供超频的效果而不需要超时钟。相关方法提供了这种有效的超频。在参数分析系统的实施例中，测试点采样元件和分析电路作为一个或多个可变延迟时基发生器的输出的函数被计时以提供各种参数分析功能。相关方法解决了这个功能。

8. 发明授权

US07315574B2 System and method for generating a jittered test signal 失效
标题翻译：用于产生抖动测试信号的系统和方法
公开(公告)号：US07315574B2
公开(公告)日：2008-01-01
申请号：US11114572
申请日：2005-04-26
申请人： Mohamed M. Hafed , Geoffrey D. Duerden , Gordon W. Roberts
发明人： Mohamed M. Hafed , Geoffrey D. Duerden , Gordon W. Roberts
IPC分类号： H04B17/00 , H04Q1/20
CPC分类号： H04B3/462 , G01R31/31709 , G01R31/31725 , G01R31/3183 , G01R31/31917
摘要： A multi-speed jittered signal generator (216, 400) that generates a full-speed jittered signal (404) by scaling a low-speed jittered signal (420) using a frequency scaler (428). The low-speed jittered signal is created by injecting a modulation signal (416) into a reference signal (412) using a jitter injector (432). Injecting jitter into a low-speed reference signal allows the full-speed jittered signal to be of higher quality than conventional jitter signals created by injecting jitter information into a full-speed reference signal. The multi-speed jittered signal generator may be used as part of a testing system (208) for testing various circuitry, such as high-speed serializer/deserializer circuitry (220).
摘要翻译：通过使用频率缩放器（428）缩放低速抖动信号（420）来产生全速抖动信号（404）的多速抖动信号发生器（216,400）。通过使用抖动注入器（432）将调制信号（416）注入参考信号（412）来创建低速抖动信号。将抖动注入低速参考信号允许全速抖动信号的质量高于通过将抖动信息注入全速参考信号而产生的传统抖动信号。多速抖动信号发生器可以用作用于测试各种电路的测试系统（208）的一部分，例如高速串行器/解串器电路（220）。

9. 发明授权

US07813297B2 High-speed signal testing system having oscilloscope functionality 有权
标题翻译：具有示波器功能的高速信号测试系统
公开(公告)号：US07813297B2
公开(公告)日：2010-10-12
申请号：US11776865
申请日：2007-07-12
申请人： Mohamed M. Hafed
发明人： Mohamed M. Hafed
IPC分类号： H04L12/26
CPC分类号： G01R31/31932 , G01R13/02 , G01R31/3193
摘要： A high-speed signal testing system that includes a digital circuitry for providing a pattern tester with oscilloscope functionality at minimal implementation cost. The digital circuitry includes a time-base generator that provides a high-speed repeating time-base signal. The time-base signal, in conjunction with a sub-sampler and an accumulation memory, allows the system to zoom in on, and analyze portions of, one or more bits of interest in a repeating pattern present on the signal under test. Such portions of interest include rising and falling edges and constant high and low bit values.
摘要翻译：一种高速信号测试系统，包括一个数字电路，用于以最低的实施成本为模式测试仪提供示波器功能。数字电路包括提供高速重复时基信号的时基发生器。时基信号与子采样器和累加存储器一起允许系统放大并分析存在于被测信号上的重复图案中的一个或多个感兴趣的位的部分。这些感兴趣的部分包括上升沿和下降沿以及恒定的高和低位值。

10. 发明申请

US20080013456A1 High-Speed Signal Testing System Having Oscilloscope Functionality 有权
标题翻译：具有示波器功能的高速信号测试系统
公开(公告)号：US20080013456A1
公开(公告)日：2008-01-17
申请号：US11776865
申请日：2007-07-12
申请人： Mohamed M. Hafed
发明人： Mohamed M. Hafed
IPC分类号： H04L12/28
CPC分类号： G01R31/31932 , G01R13/02 , G01R31/3193
摘要： A high-speed signal testing system that includes a digital circuitry for providing a pattern tester with oscilloscope functionality at minimal implementation cost. The digital circuitry includes a time-base generator that provides a high-speed repeating time-base signal. The time-base signal, in conjunction with a sub-sampler and an accumulation memory, allows the system to zoom in on, and analyze portions of, one or more bits of interest in a repeating pattern present on the signal under test. Such portions of interest include rising and falling edges and constant high and low bit values.
摘要翻译：一种高速信号测试系统，包括一个数字电路，用于以最低的实施成本为模式测试仪提供示波器功能。数字电路包括提供高速重复时基信号的时基发生器。时基信号与子采样器和累加存储器一起允许系统放大并分析存在于被测信号上的重复图案中的一个或多个感兴趣的位的部分。这些感兴趣的部分包括上升沿和下降沿以及恒定的高和低位值。

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