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1. 发明授权

US07242209B2 System and method for testing integrated circuits 失效
标题翻译：集成电路测试系统和方法
公开(公告)号：US07242209B2
公开(公告)日：2007-07-10
申请号：US10838846
申请日：2004-05-03
申请人： Gordon W. Roberts , Antonio H. Chan , Geoffrey D. Duerden , Mohamed M. Hafed , Sébastien Laberge , Bardia Pishdad , Clarence K. L. Tam
发明人： Gordon W. Roberts , Antonio H. Chan , Geoffrey D. Duerden , Mohamed M. Hafed , Sébastien Laberge , Bardia Pishdad , Clarence K. L. Tam
IPC分类号： G01R31/26
CPC分类号： G01R31/31907 , G01R31/319 , G01R31/31928
摘要： A module (236, 236′) containing an integrated testing system (108) that includes one or more measurement engines (200, 202) tightly coupled with a compute engine (208). The one or more measurement engines include at least one stimulus instrument (212) for exciting circuitry of a device-under-test (104) with one or more stimulus signals, and at least one measurement instrument (216) that measures the response of the device-under-test to the stimulus signal(s) and generates measurement data. The compute engine includes computation logic circuitry (800) for determining whether or not the circuitry aboard the device-under-test passes or fails. The integrated testing system further includes a communications engine (204) providing two-way communications between the integrated testing system automated testing equipment (116) and/or a dedicated user interface (140) residing on a host computer (136).
摘要翻译：包括集成测试系统（108）的模块（236,236'），其包括与计算引擎（208）紧密耦合的一个或多个测量引擎（200,202）。一个或多个测量引擎包括至少一个激励仪器（212），用于激励具有一个或多个激励信号的被测设备（104）的电路，以及至少一个测量仪器（216）刺激信号下测试装置，并产生测量数据。计算引擎包括计算逻辑电路（800），用于确定被测设备中的电路是否通过或失败。集成测试系统还包括在集成测试系统自动测试设备（116）和/或驻留在主计算机（136）上的专用用户界面（140）之间提供双向通信的通信引擎（204）。

2. 发明授权

US07315574B2 System and method for generating a jittered test signal 失效
标题翻译：用于产生抖动测试信号的系统和方法
公开(公告)号：US07315574B2
公开(公告)日：2008-01-01
申请号：US11114572
申请日：2005-04-26
申请人： Mohamed M. Hafed , Geoffrey D. Duerden , Gordon W. Roberts
发明人： Mohamed M. Hafed , Geoffrey D. Duerden , Gordon W. Roberts
IPC分类号： H04B17/00 , H04Q1/20
CPC分类号： H04B3/462 , G01R31/31709 , G01R31/31725 , G01R31/3183 , G01R31/31917
摘要： A multi-speed jittered signal generator (216, 400) that generates a full-speed jittered signal (404) by scaling a low-speed jittered signal (420) using a frequency scaler (428). The low-speed jittered signal is created by injecting a modulation signal (416) into a reference signal (412) using a jitter injector (432). Injecting jitter into a low-speed reference signal allows the full-speed jittered signal to be of higher quality than conventional jitter signals created by injecting jitter information into a full-speed reference signal. The multi-speed jittered signal generator may be used as part of a testing system (208) for testing various circuitry, such as high-speed serializer/deserializer circuitry (220).
摘要翻译：通过使用频率缩放器（428）缩放低速抖动信号（420）来产生全速抖动信号（404）的多速抖动信号发生器（216,400）。通过使用抖动注入器（432）将调制信号（416）注入参考信号（412）来创建低速抖动信号。将抖动注入低速参考信号允许全速抖动信号的质量高于通过将抖动信息注入全速参考信号而产生的传统抖动信号。多速抖动信号发生器可以用作用于测试各种电路的测试系统（208）的一部分，例如高速串行器/解串器电路（220）。

3. 发明授权

US06917320B2 Method and device for use in DC parametric tests 失效
标题翻译：用于直流参数测试的方法和装置
公开(公告)号：US06917320B2
公开(公告)日：2005-07-12
申请号：US10832208
申请日：2004-04-26
申请人： Gordon W. Roberts , Clarence K. L. Tam
发明人： Gordon W. Roberts , Clarence K. L. Tam
IPC分类号： G01R31/30 , G01R31/319 , H03M3/00
CPC分类号： G01R31/31924 , G01R31/3004
摘要： A system and device suitable for use in performing a DC parametric test on an external load is provided. The device may be configured to apply a desired voltage or current to the external load. The circuit device receives a forcing parameter signal at an input and releases at an output a signal approximating the forcing parameter signal to the external load. The circuit device includes a first circuit segment between the input and the output having a search unit, an intermediate voltage point and an internal load between the intermediate voltage point and the output. A second circuit segment connected in a feedback arrangement with the first circuit segment provides the search unit with the voltage at the output. The search unit is adapted for generating a second voltage signal on the basis of the forcing parameter signal and the first voltage signal received and to apply the second voltage signal to the intermediate voltage point. The application of second voltage signal to the intermediate voltage point causes a change in either one of the voltage signal or the current signal at the output such that a signal approximating the forcing parameter signal is caused at the output. A current measuring circuit adapted for providing a measure of the current at the external load suitable for use with a voltage generating circuit device is also provided.
摘要翻译：提供了适用于对外部负载执行直流参数测试的系统和设备。该设备可以被配置为向外部负载施加期望的电压或电流。电路装置在输入端接收强制参数信号，并在输出端释放逼近强制参数信号到外部负载的信号。电路装置包括在输入和输出之间的第一电路段，其具有搜索单元，中间电压点和中间电压点与输出之间的内部负载。以反馈装置与第一电路段连接的第二电路段向搜索单元提供输出端的电压。搜索单元适于基于强制参数信号和接收的第一电压信号产生第二电压信号，并将第二电压信号施加到中间电压点。向中间电压点施加第二电压信号导致在输出处的电压信号或电流信号中的任一个的变化，使得在输出处产生逼近强制参数信号的信号。还提供了一种电流测量电路，其适于提供适于与电压产生电路装置一起使用的外部负载下的电流测量。

4. 发明授权

US06727834B2 Method and device for use in DC parametric tests 失效
标题翻译：用于直流参数测试的方法和装置
公开(公告)号：US06727834B2
公开(公告)日：2004-04-27
申请号：US10427819
申请日：2003-05-01
申请人： Gordon W. Roberts , Clarence K. L. Tam
发明人： Gordon W. Roberts , Clarence K. L. Tam
IPC分类号： H03M300
CPC分类号： G01R31/31924 , G01R31/3004
摘要： A system and device suitable for use in performing a DC parametric test on an external load is provided. The device may be configured to apply a desired voltage or current to the external load. The circuit device receives a forcing parameter signal at an input and releases at an output a signal approximating the forcing parameter signal to the external load. The circuit device includes a first circuit segment between the input and the output having a search unit, an intermediate voltage point and an internal load between the intermediate voltage point and the output. A second circuit segment connected in a feedback arrangement with the first circuit segment provides the search unit with the voltage at the output. The search unit is adapted for generating a second voltage signal on the basis of the forcing parameter signal and the first voltage signal received and to apply the second voltage signal to the intermediate voltage point. The application of second voltage signal to the intermediate voltage point causes a change in either one of the voltage signal or the current signal at the output such that a signal approximating the forcing parameter signal is caused at the output. A current measuring circuit adapted for providing a measure of the current at the external load suitable for use with a voltage generating circuit device is also provided
摘要翻译：提供了适用于对外部负载执行直流参数测试的系统和设备。该设备可以被配置为向外部负载施加期望的电压或电流。电路装置在输入端接收强制参数信号，并在输出端释放逼近强制参数信号到外部负载的信号。电路装置包括在输入和输出之间的第一电路段，其具有搜索单元，中间电压点和中间电压点与输出之间的内部负载。以反馈装置与第一电路段连接的第二电路段向搜索单元提供输出端的电压。搜索单元适于基于强制参数信号和接收的第一电压信号产生第二电压信号，并将第二电压信号施加到中间电压点。向中间电压点施加第二电压信号导致在输出处的电压信号或电流信号中的任一个的变化，使得在输出处产生逼近强制参数信号的信号。还提供了一种电流测量电路，其适于提供适于与电压产生电路装置一起使用的外部负载下的电流测量

5. 发明授权

US06914548B2 Programmable DC voltage generator 失效
标题翻译：可编程直流电压发生器
公开(公告)号：US06914548B2
公开(公告)日：2005-07-05
申请号：US09844277
申请日：2001-04-30
申请人： Gordon W. Roberts , Mohamed Hafed , Sébastien Laberge
发明人： Gordon W. Roberts , Mohamed Hafed , Sébastien Laberge
IPC分类号： G05F1/10 , G05F3/02 , G06F1/025 , H03M1/82
CPC分类号： G06F1/025
摘要： An efficient technique for generating accurate on-chip DC reference voltages is based on filtering a digital pulse modulated sequence in order to extract its average value encoding a DC level, A passive on-chip filter is used for simplicity with an all-digital modulator implementation. Modulation is proposed using pulse-width and preferably pulse-density modulation methods. The latter has the advantage of using a significantly smaller filter which translates into a smaller implementation and faster operational settling times. Many digital pulse modulation generators are proposed.
摘要翻译：用于产生精确的片上直流参考电压的高效技术是基于对数字脉冲调制序列进行滤波，以便提取其编码DC电平的平均值。使用全数字调制器实现简单的无源片上滤波器。提出使用脉冲宽度优选脉冲密度调制方法进行调制。后者具有使用显着更小的滤波器的优点，其转化为更小的实现和更快的操作建立时间。提出了许多数字脉冲调制发生器。

6. 发明授权

US06850051B2 Timing measurement device using a component-invariant vernier delay line 失效
标题翻译：使用分量不变游标延迟线的定时测量装置
公开(公告)号：US06850051B2
公开(公告)日：2005-02-01
申请号：US10105434
申请日：2002-03-26
申请人： Gordon W. Roberts , Antonio H. Chan
发明人： Gordon W. Roberts , Antonio H. Chan
IPC分类号： G01R29/02 , G04F10/00 , G04F10/06 , G01R23/175
CPC分类号： G04F10/06 , G04F10/00
摘要： In recent years, much effort has been placed on improving the performance of timing and jitter measurement devices using Delay Locked Loop (DLL) and Vernier Delay Line (VDL) techniques. However, these approaches require highly matched elements in order to reduce differential non-linearity timing errors. In an attempt to reduce the requirement on element matching, a component-invariant VDL technique is disclosed that enables the measurement device to be synthesized from an RTL description. The present invention is based on a single-stage VDL structure, which is used to mimic the behavior of a complete VDL. Furthermore, as test time is an important consideration during a production test, a method and system is provided that reduces test time at the expense of additional hardware.
摘要翻译：近年来，使用延迟锁定环（DLL）和游标延迟线（VDL）技术来改善定时和抖动测量设备的性能已经付出了很多努力。然而，这些方法需要高度匹配的元件，以便减少微分非线性定时误差。为了减少对元件匹配的要求，公开了一种使得能够从RTL描述合成测量装置的分量不变的VDL技术。本发明基于单级VDL结构，其用于模拟完整VDL的行为。此外，由于测试时间是生产测试期间的重要考虑因素，所以提供了一种方法和系统，可以以额外的硬件为代价缩短测试时间。

7. 发明授权

US08849882B2 Generation of an analog Gaussian noise signal having predetermined characteristics 有权
标题翻译：产生具有预定特性的模拟高斯噪声信号
公开(公告)号：US08849882B2
公开(公告)日：2014-09-30
申请号：US12254149
申请日：2008-10-20
申请人： Sadok Aouini , Gordon W. Roberts
发明人： Sadok Aouini , Gordon W. Roberts
IPC分类号： G06F7/58 , H03B29/00
CPC分类号： H03B29/00
摘要： The present invention relates to a method and system for providing an analog Gaussian noise signal having the predetermined probability distribution function, bandwidth and center frequency. A band-limited digital noise signal indicative of a Gaussian noise signal having a predetermined Gaussian probability distribution function is ΣΔ modulated generating a pulse-density modulated 1-bit sequence representing a Gaussian noise signal having a predetermined probability distribution function, bandwidth and center frequency. Using an analog low-pass filter the pulse-density modulated 1-bit sequence is then converted into a respective analog Gaussian noise signal having the predetermined probability distribution function, bandwidth and center frequency. The method and system are successfully employed in numerous applications such as in histogram testing and probabilistic digitization.
摘要翻译：本发明涉及一种用于提供具有预定概率分布函数，带宽和中心频率的模拟高斯噪声信号的方法和系统。指示具有预定高斯概率分布函数的高斯噪声信号的带限数字噪声信号为＆Sgr;＆Dgr; 调制产生表示具有预定概率分布函数，带宽和中心频率的高斯噪声信号的脉冲密度调制1比特序列。使用模拟低通滤波器，然后将脉冲密度调制的1比特序列转换为具有预定概率分布函数，带宽和中心频率的相应模拟高斯噪声信号。该方法和系统成功应用于诸如直方图测试和概率数字化等众多应用中。

8. 发明授权

US07474974B2 Embedded time domain analyzer for high speed circuits 有权
标题翻译：嵌入式时域分析仪用于高速电路
公开(公告)号：US07474974B2
公开(公告)日：2009-01-06
申请号：US11699997
申请日：2007-01-31
申请人： Gordon W. Roberts , Mouna Safi-Harab , Mourad Oulmane
发明人： Gordon W. Roberts , Mouna Safi-Harab , Mourad Oulmane
IPC分类号： G01R29/02
CPC分类号： G01R31/31725 , G01R31/3167 , G01R31/31726
摘要： A method of providing an on-chip high-speed time domain digital analyzer for the characterization and analysis of signals within an integrated circuit is provided. The method involves processing the signal being characterized/analyzed in the digital domain irrespective of it's starting format. The approach performs a voltage-to-time conversion using predetermined voltage thresholds, applying a time amplification to the digital time information, measuring the amplified time difference between events and converting the amplified time difference as required by the characterization/analysis. The method allows the capture of very high-speed signals with high resolution without the requirements of complex and high-speed electronics. As such the on-chip high-speed time domain digital analyzer can function as an oscilloscope, pulse width analyzer, rise time analyzer and even logic analyzer. Further the method allows the capture and analysis of single and non-repetitive signal events unlike prior art approaches to time domain oscilloscopes.
摘要翻译：提供了一种提供用于集成电路内的信号的表征和分析的片上高速时域数字分析仪的方法。该方法涉及处理在数字领域中被表征/分析的信号，而不管其起始格式如何。该方法使用预定的电压阈值执行电压 - 时间转换，对数字时间信息应用时间放大，测量事件之间的放大时间差，并根据表征/分析的要求转换放大的时间差。该方法允许以高分辨率捕获非常高速的信号，而不需要复杂和高速电子设备。因此片上高速时域数字分析仪可以作为示波器，脉宽分析仪，上升时间分析仪甚至逻辑分析仪。此外，该方法允许与现有技术的时域示波器方法不同，捕获和分析单个和非重复信号事件。

9. 发明授权

US08258892B2 High-speed bandpass serial data link 有权
标题翻译：高速带通串行数据链路
公开(公告)号：US08258892B2
公开(公告)日：2012-09-04
申请号：US12388752
申请日：2009-02-19
申请人： Ramesh Abhari , Asanee Suntives , Gordon W. Roberts , Nathan Smith
发明人： Ramesh Abhari , Asanee Suntives , Gordon W. Roberts , Nathan Smith
IPC分类号： H01P5/12 , H01P3/08
CPC分类号： H01P5/107 , B82Y20/00 , G02B6/125 , H01P3/121 , H04J14/0298
摘要： The present invention relates to a method and system for high-speed bandpass serial data communication. A driver receives at least one data signal and generates a bandpass data signal for transmission through a bandpass waveguide interconnect. The bandpass data signal is launched into the bandpass waveguide interconnect using a first adaptor and extracted therefrom after transmission using a second adaptor. A receiver connected to the second adaptor recovers the at least one data signal from the extracted bandpass data signal. A dispersion compensation circuit receives one of the at least one data signal and the bandpass data signal and information indicative of a phase response of the bandpass waveguide interconnect and dispersion compensates the one of the at least one data signal and the bandpass data signal by compensating the phase response of the bandpass waveguide interconnect.
摘要翻译：本发明涉及一种用于高速带通串行数据通信的方法和系统。驱动器接收至少一个数据信号并产生带通数据信号以通过带通波导互连传输。带通数据信号使用第一适配器发射到带通波导互连中，并且在使用第二适配器传输之后从其提取。连接到第二适配器的接收器从所提取的带通数据信号恢复至少一个数据信号。色散补偿电路接收至少一个数据信号和带通数据信号中的一个以及指示带通波导互连的相位响应的信息，并且色散通过补偿至少一个数据信号和带通数据信号来补偿带通波导互连的相位响应。

10. 发明申请

US20080183409A1 Embedded time domain analyzer for high speed circuits 有权
标题翻译：嵌入式时域分析仪用于高速电路
公开(公告)号：US20080183409A1
公开(公告)日：2008-07-31
申请号：US11699997
申请日：2007-01-31
申请人： Gordon W. Roberts , Mouna Safi-Harab , Mourad Oulmane
发明人： Gordon W. Roberts , Mouna Safi-Harab , Mourad Oulmane
IPC分类号： G01R29/02
CPC分类号： G01R31/31725 , G01R31/3167 , G01R31/31726
摘要： A method of providing an on-chip high-speed time domain digital analyzer for the characterization and analysis of signals within an integrated circuit is provided. The method involves processing the signal being characterized/analyzed in the digital domain irrespective of it's starting format. The approach performs a voltage-to-time conversion using predetermined voltage thresholds, applying a time amplification to the digital time information, measuring the amplified time difference between events and converting the amplified time difference as required by the characterization/analysis. The method allows the capture of very high-speed signals with high resolution without the requirements of complex and high-speed electronics. As such the on-chip high-speed time domain digital analyzer can function as an oscilloscope, pulse width analyzer, rise time analyzer and even logic analyzer. Further the method allows the capture and analysis of single and non-repetitive signal events unlike prior art approaches to time domain oscilloscopes.
摘要翻译：提供了一种提供用于集成电路内的信号的表征和分析的片上高速时域数字分析仪的方法。该方法涉及处理在数字领域中被表征/分析的信号，而不管其起始格式如何。该方法使用预定的电压阈值执行电压 - 时间转换，对数字时间信息应用时间放大，测量事件之间的放大时间差，并根据表征/分析的要求转换放大的时间差。该方法允许以高分辨率捕获非常高速的信号，而不需要复杂和高速电子设备。因此片上高速时域数字分析仪可以作为示波器，脉宽分析仪，上升时间分析仪甚至逻辑分析仪。此外，该方法允许与现有技术的时域示波器方法不同，捕获和分析单个和非重复信号事件。

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