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    • 2. 发明授权
    • Wireless communication restriction device, repeater and base station
    • 无线通信限制设备,中继器和基站
    • US06987978B2
    • 2006-01-17
    • US10337310
    • 2003-01-07
    • Noboru MasudaTakashi YanoTakeshi Kato
    • Noboru MasudaTakashi YanoTakeshi Kato
    • H04M1/00
    • H04B7/1555H04B7/2606H04W84/005H04W84/047
    • The disclosed invention makes mobile terminals physically impossible to use in specific spaces without using radio waves of so high intensity as to affect medical devices and without requiring telephone companies that operate wireless communications systems (WCS) to take special measures. Cooperation of a telephone company on the implementation of making mobile terminals physically impossible to use in specific spaces makes mobile terminals provided by the telephone company easy to use. Pseudo signals of downlink pilot signal in WCS are emitted off the pilot timing in specific spaces. Uplink channel radio waves in cooperative telephone compannies' WCS are relayed and communication path is disconnected if the uplink channel radio waves are for communication of an attribute banned in the space. Communication path can be disconnected without increasing the intensity of radio waves so high. In cooperative telephone compannies' WCS, only the path of communication of an attribute banned in the space is disconnected.
    • 所公开的发明使得移动终端在特定空间中物理上不可能使用,而不使用如此高的强度的无线电波影响医疗设备,并且不需要操作无线通信系统(WCS)的电话公司采取特殊措施。 电话公司在实施移动终端实际上​​不可能在特定空间中使用的合作使得电话公司提供的移动终端易于使用。 WCS中的下行链路导频信号的伪信号在特定空间内从导频定时发出。 如果上行链路信道无线电波用于在空间中禁止的属性的通信,则中继合作电话单元WCS中的上行链路无线电波,并且通信路径被断开。 通信路径可以在不增加无线电波强度的情况下断开连接。 在合作电话公司的WCS中,只有空间中禁止的属性的通信路径才会断开连接。
    • 3. 发明授权
    • Logic circuit
    • 逻辑电路
    • US6064234A
    • 2000-05-16
    • US134335
    • 1998-08-14
    • Noboru MasudaYoshio MikiShun Kawabe
    • Noboru MasudaYoshio MikiShun Kawabe
    • H03K19/0948H03K19/094
    • H03K19/0948
    • A logic circuit for use as a selector having multiple inputs and high operation speed. The logic circuit includes a first FET having a first electrode connected to a first power supply, a second electrode connected to an output terminal and a third electrode connected to an intermediate control node, and a plurality of logic blocks parallelly connected between the second power supply and the output terminal. Each logic block includes second and third FETs being of a conductivity type opposite to that of the first FET and connected in series between the output terminal and a second power supply. Each logic block also includes a fourth FET being of the same conductivity type as the second and third FETs and having a third electrode connected to the third electrode of the second FET, a first electrode connected to the third electrode of the third FET and a second electrode connected to the intermediate control node. The conduction resistance between the output terminal and the first power supply is reduced and the parasitic capacitance added to the output terminal is also reduced, thereby allowing the logic circuit to be operated at high speed.
    • 用作具有多个输入和高操作速度的选择器的逻辑电路。 逻辑电路包括:第一FET,具有连接到第一电源的第一电极,连接到输出端子的第二电极和连接到中间控制节点的第三电极;以及并联连接在第二电源 和输出端子。 每个逻辑块包括具有与第一FET相反的导电类型的第二和第三FET,并串联连接在输出端和第二电源之间。 每个逻辑块还包括与第二和第三FET具有相同导电类型的第四FET,并且具有连接到第二FET的第三电极的第三电极,连接到第三FET的第三电极的第一电极和第二FET 电极连接到中间控制节点。 输出端子与第一电源之间的导通电阻降低,并且增加到输出端子的寄生电容也减小,从而允许逻辑电路以高速运行。
    • 6. 发明授权
    • Apparatus for matching impedance in an electrostatic sensor
    • 用于匹配静电传感器中的阻抗的装置
    • US5325067A
    • 1994-06-28
    • US67393
    • 1993-05-25
    • Noboru MasudaTetsuo OosawaYasutaka Fujii
    • Noboru MasudaTetsuo OosawaYasutaka Fujii
    • G01R29/24G01R27/26H03K17/955
    • H03K17/955G01R27/2688
    • It is an object of the present invention to prevent variations in sensitivity of the sensor circuits of the respective channels by equalizing the power of oscillation frequency signals to be distributed/supplied from one oscillation circuit to the sensor circuits of the respective channels. Multi-channel sensor circuits are arranged with a common oscillation circuit. A high-impedance conversion circuit is connected to the output terminal of the oscillation circuit. A first impedance matching circuit for performing impedance matching of resonance circuits of the respective channels with reference to the oscillation circuit is arranged on the output side of the high-impedance conversion circuit. Second impedance matching circuits for performing impedance matching of the oscillation circuit with reference to the resonance circuits are connected at the input terminals of the resonance circuits of the respective channels. The first impedance matching circuit is connected to the second impedance matching circuits through coaxial cables.
    • 本发明的目的是通过将从一个振荡电路分配/提供的振荡频率信号的功率均衡到各个通道的传感器电路来防止各个通道的传感器电路的灵敏度的变化。 多通道传感器电路配有一个共同的振荡电路。 高阻抗转换电路连接到振荡电路的输出端。 在高阻抗转换电路的输出侧配置有用于根据振荡电路进行各通道的谐振电路的阻抗匹配的第一阻抗匹配电路。 用于相对于谐振电路执行振荡电路的阻抗匹配的第二阻抗匹配电路连接在各个通道的谐振电路的输入端。 第一阻抗匹配电路通过同轴电缆连接到第二阻抗匹配电路。
    • 8. 发明授权
    • Clock signal supply system
    • 时钟信号供电系统
    • US5184027A
    • 1993-02-02
    • US688696
    • 1991-04-22
    • Noboru MasudaRyotaro KamikawaiMasayoshi YagyuMasakazu YamamotoHiroyuki ItohTatsuya Saito
    • Noboru MasudaRyotaro KamikawaiMasayoshi YagyuMasakazu YamamotoHiroyuki ItohTatsuya Saito
    • C04B35/45G06F1/10H01L39/12H01L39/24
    • C04B35/4504G06F1/10H01L39/126H01L39/2419
    • A clock signal supply system provides for automatic accurate phase adjustment of clock signals. The system includes an oscillator that produces clock signals and a reference generator that generates a reference signal that has a predetermined relationship with respect to the clock signals produced by the oscillator. At each location where the clock signal is to be received, an adjusting circuit is provided to adjust the phase of the received clock signals. Such an adjusting circuit may include a variable delay circuit which receives the clock signal and produces an output which is constituted by the clock signal having a varied delay, to the remainder of the attached circuits. Further, the output of the variable delay is fed back to a phase difference detection circuit. The reference signal is second input to the phase difference detection circuit. This phase difference detection circuit compares the difference of the reference signal and the output of the variable delay circuit and produces the control signal to the variable delay circuit which will further adjust the phase of the clock signal that is received. This adjustment is carried out at each of the locations where the clock signal is to be received, thereby providing automatic adjustment of the phase of the clock signals.
    • 时钟信号供应系统提供时钟信号的自动精确相位调整。 该系统包括产生时钟信号的振荡器和产生相对于由振荡器产生的时钟信号具有预定关系的参考信号的参考发生器。 在要接收时钟信号的每个位置,提供调整电路以调整所接收的时钟信号的相位。 这种调整电路可以包括可变延迟电路,其接收时钟信号并且产生由具有变化的延迟的时钟信号构成的输出到连接电路的其余部分。 此外,可变延迟的输出被反馈到相位差检测电路。 参考信号是相位差检测电路的第二输入。 该相位差检测电路比较参考信号和可变延迟电路的输出的差异,并将该控制信号产生到可变延迟电路,该可变延迟电路将进一步调节所接收的时钟信号的相位。 该调整是在要接收时钟信号的每个位置处执行的,从而提供对时钟信号的相位的自动调整。