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    • 1. 发明申请
    • POWER SEMICONDUCTOR DEVICE
    • 功率半导体器件
    • US20160372585A1
    • 2016-12-22
    • US15122261
    • 2014-10-29
    • MITSUBISHI ELECTRIC CORPORATION
    • Akihiko FURUKAWAShoichi ORITAHiroki MURAOKAAtsushi NARAZAKITsuyoshi KAWAKAMIYuji MURAKAMI
    • H01L29/739H01L29/08H01L29/10H01L29/66
    • H01L29/7397H01L29/0619H01L29/0696H01L29/0804H01L29/0821H01L29/1004H01L29/1095H01L29/407H01L29/66348
    • In the present application, a power semiconductor device includes a first-conductive-type first base region having a first principal surface and a second principal surface opposite to the first principal surface, a second-conductive-type second base region disposed on the first principal surface and at least three groove parts parallel to each other disposed from a surface of the second base region. The device further includes insulating films covering inner walls of the respective groove parts, conductive trench gates filled on the insulating films, a first-conductive-type emitter region disposed in the second base region, and a second-conductive-type collector region disposed on the second principal surface of the first base region. The trench gates embedded in the first groove part and the third groove part are electrically connected to the gate electrode, and the trench gate embedded in the second groove part is electrically connected to the emitter electrode.
    • 在本申请中,功率半导体器件包括具有第一主表面和与第一主表面相对的第二主表面的第一导电类型的第一基极区域,设置在第一主体上的第二导电型第二基极区域 表面和至少三个彼此平行的凹槽部分,其设置在第二基底区域的表面上。 该装置还包括覆盖各个沟槽部分的内壁的绝缘膜,填充在绝缘膜上的导电沟槽栅极,设置在第二基极区域中的第一导电型发射极区域和设置在第二导电型集电极区域上的第二导电型集电极区域 第一基区的第二主表面。 嵌入第一沟槽部分和第三沟槽部分中的沟槽栅电连接到栅电极,并且嵌入在第二沟槽部分中的沟槽栅电连接到发射极。