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1. 发明授权

US08054670B2 Reconfiguration controlling apparatus for optically reconfigurable gate array and method thereof 有权
标题翻译：用于光可重构门阵列的重配置控制装置及其方法
公开(公告)号：US08054670B2
公开(公告)日：2011-11-08
申请号：US12310487
申请日：2007-08-01
申请人： Minoru Watanabe , Fuminori Kobayashi
发明人： Minoru Watanabe , Fuminori Kobayashi
IPC分类号： G11C13/04
CPC分类号： H03K19/173
摘要： [PROBLEMS] To provide a reconfiguration controller of an optically reconfigurable gate array for correctly and reliably writing various types of logical operation circuits of an optically reconfigurable gate array and performing high-speed logical operation by quickly starting up the circuits. [MEANS FOR SOLVING PROBLEMS] A reconfiguration controller comprises a laser array (1) for producing a laser beam (1a) to serve as a reproducing beam and applying the laser beam (1a), a hologram memory (2) for outputting an optical pattern (2a) when receiving the laser beam (1a) according to pre-stored recording information and outputting a control signal light (2b) relating to optical reconfiguration by the optical pattern (2a), an optically reconfigurable gate array (3) for reconfiguring arrayed logical operation cells into various logical operation circuits according to the outputted optical pattern (2a), and outputting an optical control signal (S3) from the control signal light (2b), and a reproduction light application control means (4) for controlling the application of the laser beam (1a) emitted from the laser array (1) according to the optical control signal. Therefore, optical pattern application can be performed according to the optical control signal at a reconfiguration time adapted to any of various logical operation circuits sequentially reconfigured by the optically reconfigurable gate array. Consequently, correct and reliable write of any one of various types of logical operation circuits can be performed without any write error, and such various types of logical operation circuits can perform logical operation sequentially at high speed.
摘要翻译：提供一种光学可重构门阵列的重新配置控制器，用于正确且可靠地写入光学可重构门阵列的各种类型的逻辑运算电路，并通过快速启动电路来执行高速逻辑运算。解决问题的手段重新配置控制器包括用于产生激光束（1a）以用作再现光束并施加激光束（1a）的激光阵列（1），用于输出光学图案的全息存储器（2）（2a），当根据预先存储的记录信息接收激光束（1a）并且输出与所述光学图案（2a）相关的光学重新配置的控制信号光（2b）时，用于重配置的光学可重构门阵列（3）根据输出的光学图案（2a）将逻辑运算单元转换成各种逻辑运算电路，并从控制信号光（2b）输出光控制信号（S3）;以及再现光应用控制单元（4），用于控制应用根据光学控制信号从激光阵列（1）发射的激光束（1a）。因此，可以根据光控制信号，在适于由光学可重构门阵列顺序重新配置的各种逻辑运算电路中的任何一个的重新配置时间执行光学图案应用。因此，可以执行各种类型的逻辑运算电路中的任一种的正确可靠的写入而没有任何写入错误，并且这种各种类型的逻辑运算电路可以高速顺序地执行逻辑运算。

2. 发明申请

US20090296178A1 Optically reconfigurable logic circuit 有权
标题翻译：光学可重构逻辑电路
公开(公告)号：US20090296178A1
公开(公告)日：2009-12-03
申请号：US11597474
申请日：2005-05-11
申请人： Minoru Watanabe , Fuminori Kobayashi
发明人： Minoru Watanabe , Fuminori Kobayashi
IPC分类号： G02F3/00
CPC分类号： H03K19/17748 , H01L27/1446
摘要： To provide an optically reconfigurable logic circuit in which a mount area of an optical circuit is reduced as much as possible and a high gate density is realized.In an optically reconfigurable logic circuit 1 provided with a plurality of configuration information input circuits 6 for converting an optical signal including logic circuit configuration information into an electric signal and holding and outputting this electric signal and a logic configuration variable circuit 7 for performing logic configuration on the basis of the logic circuit configuration information, the configuration information input circuits 6 holds the logic circuit configuration information as electric charge with use of a junction capacitance and a floating capacitance of a photoconductive device P. An inter-terminal voltage of the photoconductive device P is converted into binary data by a binary circuit and output as a circuit configuration signal. Then, the logic configuration variable circuit 7 is configured to execute a logic arithmetic processing before the inter-terminal voltage of the photoconductive device P drops to be equal to or lower than a logic threshold of the binary circuit due to a leak current.
摘要翻译：提供光可重构逻辑电路，其中尽可能减少光电路的安装面积并实现高栅极密度。在具有多个配置信息输入电路6的光学可重构逻辑电路1中，用于将包括逻辑电路配置信息的光信号转换为电信号并保持并输出该电信号，以及用于执行逻辑配置的逻辑配置可变电路7 在逻辑电路配置信息的基础上，配置信息输入电路6使用结电容和感光体P的浮动电容将逻辑电路配置信息保持为电荷。光导器件P的端子间电压通过二进制电路转换成二进制数据并作为电路配置信号输出。然后，逻辑配置可变电路7被配置为在光电导器件P的端子间电压下降到等于或低于由于泄漏电流引起的二进制电路的逻辑阈值之前执行逻辑运算处理。

3. 发明授权

US07508234B2 Optically reconfigurable gate array write state inspection method, write state inspection device, and optically reconfigurable gate array 有权
标题翻译：光学可重构门阵列写状态检查方法，写状态检测装置和光可重构门阵列
公开(公告)号：US07508234B2
公开(公告)日：2009-03-24
申请号：US11629750
申请日：2005-06-16
申请人： Minoru Watanabe , Fuminori Kobayashi
发明人： Minoru Watanabe , Fuminori Kobayashi
IPC分类号： H01L25/00 , H03K19/177 , H03K17/693
CPC分类号： H03K19/17748 , G01R31/31728 , G01R31/318516
摘要： A technology for inspecting a write state without requiring a dedicated circuit for write state inspection of a local circuit in an ORGA. Upon switching an optical signal to be irradiated on an optically reconfigurable bit element as an inspection target from ON to OFF, in the logical circuit structure of the ORGA, first and second optical signal patterns having the optical signal ON/OFF to be irradiated to the optically reconfigurable bit element serving as optical signal patterns configuring the logical structure in which at least one logical level or output impedance changes are sequentially irradiated and input to the logical circuit. In addition, an output-state detection circuit that is connected to the logical output terminals and detects whether the logical level of the output terminal is at an H level, L level, or high impedance detects the output state.
摘要翻译：用于检查写入状态的技术，而不需要用于ORGA中本地电路的写入状态检查的专用电路。在将要照射在作为检查对象的光学可重构位元件的光信号从ON切换到OFF时，在ORGA的逻辑电路结构中，将具有光信号ON / OFF的第一和第二光信号图案照射到用作构成其中至少一个逻辑电平或输出阻抗改变的逻辑结构的光信号模式的光可重构位元件被顺序照射并输入到逻辑电路。另外，输出状态检测电路与逻辑输出端子连接，检测输出端子的逻辑电平是否为H电平，L电平或高阻抗，检测输出状态。

4. 发明申请

US20080030225A1 Optically Reconfigurable Gate Array Write State Inspection Method, Write State Inspection Device, and Optically Reconfigurable Gate Array 有权
标题翻译：光学可重构门阵列写状态检测方法，写状态检测装置和光可重构门阵列
公开(公告)号：US20080030225A1
公开(公告)日：2008-02-07
申请号：US11629750
申请日：2005-06-16
申请人： Minoru Watanabe , Fuminori Kobayashi
发明人： Minoru Watanabe , Fuminori Kobayashi
IPC分类号： H03K19/173
CPC分类号： H03K19/17748 , G01R31/31728 , G01R31/318516
摘要： To provide a technology for inspecting a write state without requiring a dedicated circuit for write state inspection of a logical circuit in an ORGA. Upon switching an optical signal to be irradiated an optically reconfigurable bit element as an inspection target from ON to OFF, in the logical circuit structure of the ORGA, first and second optical signal patterns having the optical signal ON/OFF to be irradiated to the optically reconfigurable bit element serving as optical signal patterns configuring the logical structure in which at least one logical level or output impedance changes are sequentially irradiated and input to the logical circuit. In addition, an output-state detection circuit that is connected to the logical output terminals and detects whether the logical level of the output terminal is at eh H level, L level, or high impedance detects the output state. By comparing the detected state with the normal output state of the input optical signal pattern, it is judged whether the information write state of the optically reconfigurable bit element with the optical signal is successful or unsuccessful.
摘要翻译：提供用于检查写入状态的技术，而不需要用于ORGA中的逻辑电路的写入状态检查的专用电路。在将要被照射的光信号作为检查对象从ON切换到OFF时，在ORGA的逻辑电路结构中，将具有光信号ON / OFF的第一和第二光信号图案照射到光学可配置的位元素用作配置至少一个逻辑电平或输出阻抗改变的逻辑结构的光信号模式，并顺序地照射并输入到逻辑电路。另外，连接到逻辑输出端子并检测输出端子的逻辑电平是否处于eh H电平，L电平或高阻抗的输出状态检测电路检测输出状态。通过将检测到的状态与输入光信号图案的正常输出状态进行比较，判断光学可重构位元件与光信号的信息写入状态是成功还是不成功。

5. 发明授权

US07876483B2 Optically reconfigurable logic circuit 有权
标题翻译：光学可重构逻辑电路
公开(公告)号：US07876483B2
公开(公告)日：2011-01-25
申请号：US11597474
申请日：2005-05-11
申请人： Minoru Watanabe , Fuminori Kobayashi
发明人： Minoru Watanabe , Fuminori Kobayashi
IPC分类号： G02F3/00 , H01L27/118
CPC分类号： H03K19/17748 , H01L27/1446
摘要： To provide an optically reconfigurable logic circuit in which a mount area of an optical circuit is reduced as much as possible and a high gate density is realized.In an optically reconfigurable logic circuit 1 provided with a plurality of configuration information input circuits 6 for converting an optical signal including logic circuit configuration information into an electric signal and holding and outputting this electric signal and a logic configuration variable circuit 7 for performing logic configuration on the basis of the logic circuit configuration information, the configuration information input circuits 6 holds the logic circuit configuration information as electric charge with use of a junction capacitance and a floating capacitance of a photoconductive device P. An inter-terminal voltage of the photoconductive device P is converted into binary data by a binary circuit and output as a circuit configuration signal. Then, the logic configuration variable circuit 7 is configured to execute a logic arithmetic processing before the inter-terminal voltage of the photoconductive device P drops to be equal to or lower than a logic threshold of the binary circuit due to a leak current.
摘要翻译：提供光可重构逻辑电路，其中尽可能减少光电路的安装面积并实现高栅极密度。在具有多个配置信息输入电路6的光学可重构逻辑电路1中，用于将包括逻辑电路配置信息的光信号转换为电信号并保持并输出该电信号，以及用于执行逻辑配置的逻辑配置可变电路7 在逻辑电路配置信息的基础上，配置信息输入电路6使用结电容和感光体P的浮动电容将逻辑电路配置信息保持为电荷。光导器件P的端子间电压通过二进制电路转换成二进制数据并作为电路配置信号输出。然后，逻辑配置可变电路7被配置为在光电导器件P的端子间电压下降到等于或低于由于泄漏电流引起的二进制电路的逻辑阈值之前执行逻辑运算处理。

6. 发明申请

US20100002551A1 Reconfiguration controlling apparatus for optically reconfigurable gate array and method thereof 有权
标题翻译：用于光可重构门阵列的重配置控制装置及其方法
公开(公告)号：US20100002551A1
公开(公告)日：2010-01-07
申请号：US12310487
申请日：2007-08-01
申请人： Minoru Watanabe , Fuminori Kobayashi
发明人： Minoru Watanabe , Fuminori Kobayashi
IPC分类号： G11B20/00 , G11B7/00
CPC分类号： H03K19/173
摘要： To provide a reconfiguration controller of an optically reconfigurable gate array for correctly and reliably writing various types of logical operation circuits of an optically reconfigurable gate array and performing high-speed logical operation by quickly starting up the circuits. [MEANS FOR SOLVING PROBLEMS] A reconfiguration controller comprises a laser array (1) for producing a laser beam (1a) to serve as a reproducing beam and applying the laser beam (1a), a hologram memory (2) for outputting an optical pattern (2a) when receiving the laser beam (1a) according to pre-stored recording information and outputting a control signal light (2b) relating to optical reconfiguration by the optical pattern (2a), an optically reconfigurable gate array (3) for reconfiguring arrayed logical operation cells into various logical operation circuits according to the outputted optical pattern (2a), and outputting an optical control signal (S3) from the control signal light (2b), and a reproduction light application control means (4) for controlling the application of the laser beam (1a) emitted from the laser array (1) according to the optical control signal. Therefore, optical pattern application can be performed according to the optical control signal at a reconfiguration time adapted to any of various logical operation circuits sequentially reconfigured by the optically reconfigurable gate array. Consequently, correct and reliable write of any one of various types of logical operation circuits can be performed without any write error, and such various types of logical operation circuits can perform logical operation sequentially at high speed.
摘要翻译：提供光学可重构门阵列的重新配置控制器，用于正确可靠地写入光学可重构门阵列的各种类型的逻辑运算电路，并通过快速启动电路来执行高速逻辑运算。解决问题的手段重新配置控制器包括用于产生激光束（1a）以用作再现光束并施加激光束（1a）的激光阵列（1），用于输出光学图案的全息存储器（2）（2a），当根据预先存储的记录信息接收激光束（1a）并且输出与所述光学图案（2a）相关的光学重新配置的控制信号光（2b）时，用于重配置的光学可重构门阵列（3）根据输出的光学图案（2a）将逻辑运算单元转换成各种逻辑运算电路，并从控制信号光（2b）输出光控制信号（S3）;以及再现光应用控制单元（4），用于控制应用根据光学控制信号从激光阵列（1）发射的激光束（1a）。因此，可以根据光控制信号，在适于由光学可重构门阵列顺序重新配置的各种逻辑运算电路中的任何一个的重新配置时间执行光学图案应用。因此，可以执行各种类型的逻辑运算电路中的任一种的正确可靠的写入而没有任何写入错误，并且这种各种类型的逻辑运算电路可以高速顺序地执行逻辑运算。

7. 发明授权

US09190437B2 Semiconductor detection apparatus capable of switching capacitance among different levels, and detection system including the apparatus 有权
标题翻译：能够切换不同层次的电容的半导体检测装置，以及包括该装置的检测系统
公开(公告)号：US09190437B2
公开(公告)日：2015-11-17
申请号：US13610472
申请日：2012-09-11
申请人： Jun Kawanabe , Chiori Mochizuki , Minoru Watanabe , Masato Ofuji , Keigo Yokoyama , Kentaro Fujiyoshi , Hiroshi Wayama
发明人： Jun Kawanabe , Chiori Mochizuki , Minoru Watanabe , Masato Ofuji , Keigo Yokoyama , Kentaro Fujiyoshi , Hiroshi Wayama
IPC分类号： H01J40/14 , H01L27/146
CPC分类号： H01L27/14609 , H01L27/14665
摘要： A detection apparatus includes a transistor disposed on a substrate, a conversion element disposed above the transistor and connected to the transistor, a capacitor connected in parallel with conversion element to the transistor, the capacitor including, between the substrate and the conversion element, an ohmic contact part connected to the conversion element, a semiconductor part connected to the ohmic contact part, and an electrically conductive part disposed at a location opposite to the semiconductor part and the ohmic contact part via an insulating layer, and a potential supplying unit configured to selectively supply a first electric potential to the electrically conductive part to accumulate charge carriers in the semiconductor part and a second electric potential to the electrically conductive part to deplete the semiconductor part. The detection apparatus configured in the above-described manner is capable of controlling pixel capacitance thereby achieving a high signal-to-noise ratio.
摘要翻译：检测装置包括设置在基板上的晶体管，设置在晶体管上方并连接到晶体管的转换元件，与转换元件并联连接到晶体管的电容器，电容器包括在基板和转换元件之间的欧姆连接到转换元件的接触部分，连接到欧姆接触部分的半导体部分和经由绝缘层设置在与半导体部分和欧姆接触部分相对的位置处的导电部分，以及电位供给单元，被配置为选择性地向导电部分提供第一电位，以将半导体部件中的电荷载流子积累，并且向导电部件累积第二电位以耗尽半导体部件。以上述方式配置的检测装置能够控制像素电容，从而实现高的信噪比。

8. 发明授权

US08446495B2 Image pickup apparatus and image pickup system 有权
标题翻译：摄像设备和摄像系统
公开(公告)号：US08446495B2
公开(公告)日：2013-05-21
申请号：US12912690
申请日：2010-10-26
申请人： Chiori Mochizuki , Minoru Watanabe , Takamasa Ishii , Jun Kawanabe , Kentaro Fujiyoshi
发明人： Chiori Mochizuki , Minoru Watanabe , Takamasa Ishii , Jun Kawanabe , Kentaro Fujiyoshi
IPC分类号： H04N5/217 , G01D18/00
CPC分类号： H04N5/32 , H04N5/361 , H04N5/374
摘要： In an image pickup apparatus including a plurality of pixels arranged a matrix of rows and columns, a correction unit performs a correction process based on an electric signal output via a first switch element of a particular pixel and a correction electric signal output via a second switch element of the particular pixel. A correction image signal based on the correction electric signal output via the second switch element is acquired in a period that partially overlaps in time a period in which an image signal based on the electric signal output via the first switch element is acquired. When the electric signal associated with the image signal is output for the particular pixel, the second switch element of the particular pixel is controlled to be in an on-state over a period during which the first switch element of the particular pixel is in an off-state.
摘要翻译：在包括排列成行和列的矩阵的多个像素的图像拾取装置中，校正单元基于经由特定像素的第一开关元件输出的电信号和经由第二开关输出的校正电信号来执行校正处理特定像素的元素。基于经由第二开关元件输出的校正电信号的校正图像信号在获取基于经由第一开关元件输出的电信号的图像信号的时间段的时间部分重叠的时段中被获取。当针对特定像素输出与图像信号相关联的电信号时，特定像素的第二开关元件在特定像素的第一开关元件处于关闭状态的一段时间内被控制为导通状态 -州。

9. 发明申请

US20120306041A1 DETECTION DEVICE MANUFACTURING METHOD, DETECTION DEVICE, AND DETECTION SYSTEM 有权
标题翻译：检测装置制造方法，检测装置和检测系统
公开(公告)号：US20120306041A1
公开(公告)日：2012-12-06
申请号：US13477401
申请日：2012-05-22
申请人： Kentaro Fujiyoshi , Chiori Mochizuki , Minoru Watanabe , Masato Ofuji , Keigo Yokoyama , Jun Kawanabe , Hiroshi Wayama
发明人： Kentaro Fujiyoshi , Chiori Mochizuki , Minoru Watanabe , Masato Ofuji , Keigo Yokoyama , Jun Kawanabe , Hiroshi Wayama
IPC分类号： H01L31/0224
CPC分类号： H01L27/1461 , H01L27/1462 , H01L27/14676 , H01L27/14685 , H01L27/14692
摘要： In a method of manufacturing a detection device including pixels on a substrate, each pixel including a switch element and a conversion element including an impurity semiconductor layer on an electrode, which is disposed above the switch element and isolated per pixel, the switch element and the electrode being connected in a contact hole formed in a protection layer and an interlayer insulating layer, which are disposed between the switch elements and the electrodes, the method includes forming insulating members over the interlayer insulating layer between the electrodes in contact with the interlayer insulating layer, forming an impurity semiconductor film covering the insulating members and the electrodes, and forming a coating layer covering an area of the protection layer where an orthographically-projected image of a portion of the electrode is positioned, the portion including a level difference within the contact hole.
摘要翻译：在制造包括衬底上的像素的检测装置的方法中，每个像素包括开关元件和包括电极上的杂质半导体层的转换元件，该电容器设置在开关元件上方并且每像素隔离开关元件和电极被连接在形成在保护层和层间绝缘层中的接触孔中，所述接触孔设置在开关元件和电极之间，该方法包括在与层间绝缘层接触的电极之间的层间绝缘层上形成绝缘构件形成覆盖所述绝缘构件和所述电极的杂质半导体膜，以及形成覆盖所述电极的一部分的正投影像的所述保护层的区域的覆盖层，所述部分包括所述触点内的电平差孔。

10. 发明申请

US20120305785A1 DETECTION DEVICE MANUFACTURING METHOD, DETECTION DEVICE, AND DETECTION SYSTEM 有权
标题翻译：检测装置制造方法，检测装置和检测系统
公开(公告)号：US20120305785A1
公开(公告)日：2012-12-06
申请号：US13477472
申请日：2012-05-22
申请人： Kentaro Fujiyoshi , Chiori Mochizuki , Minoru Watanabe , Masato Ofuji , Keigo Yokoyama , Jun Kawanabe , Hiroshi Wayama
发明人： Kentaro Fujiyoshi , Chiori Mochizuki , Minoru Watanabe , Masato Ofuji , Keigo Yokoyama , Jun Kawanabe , Hiroshi Wayama
IPC分类号： G01T1/24 , H01L27/14 , H01L31/18
CPC分类号： H01L27/14687 , H01L27/14609 , H01L27/1463 , H01L27/14676
摘要： In a method of manufacturing a detection device including a plurality of pixels arrayed on a substrate, the pixels each including a switch element and a conversion element including an impurity semiconductor layer disposed on an electrode, which is disposed above the switch element, which is isolated per pixel, and which is made of a transparent conductive oxide joined to the switch element, and further including an interlayer insulating layer, which is made of an organic material, which is disposed between the switch elements and the electrodes, and which covers the switch elements, the method includes insulating members each made of an inorganic material and disposed to cover the interlayer insulating layer between adjacent two of the electrodes in contact with the interlayer insulating layer, and forming an impurity semiconductor film covering the insulating members and the electrodes and becoming the impurity semiconductor layer.
摘要翻译：在制造包括排列在基板上的多个像素的检测装置的方法中，每个像素包括开关元件和转换元件，转换元件包括设置在开关元件上方的电极上的杂质半导体层，该杂质半导体层被隔离并且由连接到开关元件的透明导电氧化物制成，并且还包括设置在开关元件和电极之间的由有机材料制成并且覆盖开关的层间绝缘层元件，该方法包括各自由无机材料制成的绝缘构件，并设置成覆盖与层间绝缘层接触的相邻的两个电极之间的层间绝缘层，并且形成覆盖绝缘构件和电极的杂质半导体膜，并成为杂质半导体层。

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