专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5404412A Optical waveguide device 失效
标题翻译：光波导器件
公开(公告)号：US5404412A
公开(公告)日：1995-04-04
申请号：US996684
申请日：1992-12-24
申请人： Minoru Seino , Tadao Nakazawa , Takashi Yamane , Yoshinobu Kubota , Masaharu Doi , Kunio Sugeta , Teruo Kurahashi
发明人： Minoru Seino , Tadao Nakazawa , Takashi Yamane , Yoshinobu Kubota , Masaharu Doi , Kunio Sugeta , Teruo Kurahashi
IPC分类号： G02B6/12 , G02F1/01 , G02F1/035 , G02B5/174
CPC分类号： G02F1/035 , G02F1/0123 , G02F2201/07 , G02F2203/21
摘要： This invention aims at providing an optical waveguide device capable of stably operating for an extended period of time. The optical waveguide device comprises an optical waveguide path formed inside a surface of an electro-optical substrate, a buffer layer formed on the optical waveguide path, and a driving electrode for impressing an electric field so as to change a refractive index of the optical waveguide path, wherein the buffer layer is made of a transparent dielectric or insulator of a mixture between silicon dioxide and an oxide of at least one element selected from the group consisting of the metal elements of the Groups III to VIII, Ib and IIb of the Periodic Table and semiconductor elements other than silicon, or a transparent dielectric or insulator of an oxide between silicon and at least one of the metal elements and semiconductor elements described above.
摘要翻译：本发明的目的在于提供能够长时间稳定运行的光波导装置。光波导装置包括形成在电光基板的表面内的光波导路径，形成在光波导路径上的缓冲层，以及用于施加电场以驱动光波导的折射率的驱动电极路径，其中所述缓冲层由二氧化硅和至少一种元素的氧化物之间的混合物的透明电介质或绝缘体制成，所述至少一种元素选自元素周期表III-VIII，Ib和IIb族的金属元素除了硅之外的表格和半导体元件，或硅与至少一个上述金属元件和半导体元件之间的氧化物的透明电介质或绝缘体。

2. 发明授权

US5680497A Optical waveguide device 失效
标题翻译：光波导器件
公开(公告)号：US5680497A
公开(公告)日：1997-10-21
申请号：US350894
申请日：1994-12-07
申请人： Minoru Seino , Tadao Nakazawa , Takashi Yamane , Yoshinobu Kubota , Masaharu Doi , Kunio Sugeta , Teruo Kurahashi
发明人： Minoru Seino , Tadao Nakazawa , Takashi Yamane , Yoshinobu Kubota , Masaharu Doi , Kunio Sugeta , Teruo Kurahashi
IPC分类号： G02B6/12 , G02F1/01 , G02F1/035 , G02B6/10
CPC分类号： G02F1/035 , G02F1/0123 , G02F2201/07 , G02F2203/21
摘要： This invention aims at providing an optical waveguide device capable of stably operating for an extended period of time. The optical waveguide device comprises an optical waveguide path formed inside a surface of an electro-optical substrate, a buffer layer formed on the optical waveguide path, and a driving electrode for impressing an electric field so as to change a refractive index of the optical waveguide path, wherein the buffer layer is made of a transparent dielectric or insulator of a mixture between silicon dioxide and an oxide of at least one element selected from the group consisting of the metal elements of the Groups III to VIII, Ib and IIb of the Periodic Table and semiconductor elements other than silicon, or a transparent dielectric or insulator of an oxide between silicon and at least one of the metal elements and semiconductor elements described above.
摘要翻译：本发明的目的在于提供能够长时间稳定运行的光波导装置。光波导装置包括形成在电光基板的表面内的光波导路径，形成在光波导路径上的缓冲层，以及用于施加电场以驱动光波导的折射率的驱动电极路径，其中所述缓冲层由二氧化硅和至少一种元素的氧化物之间的混合物的透明电介质或绝缘体制成，所述至少一种元素选自元素周期表III-VIII，Ib和IIb族的金属元素除了硅之外的表格和半导体元件，或硅与至少一个上述金属元件和半导体元件之间的氧化物的透明电介质或绝缘体。

3. 发明授权

US07947547B2 Method for manufacturing a semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US07947547B2
公开(公告)日：2011-05-24
申请号：US12137807
申请日：2008-06-12
申请人： Teruo Kurahashi , Manabu Sakamoto , Yasuyoshi Mishima
发明人： Teruo Kurahashi , Manabu Sakamoto , Yasuyoshi Mishima
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842
摘要： A semiconductor device fabrication method by which CMOS transistors with low-resistance metal gate electrodes each having a proper work function can be fabricated. A HfN layer in which nitrogen concentration in an nMOS transistor formation region differs from nitrogen concentration in a pMOS transistor formation region is formed. A MoN layer is formed over the HfN layer and heat treatment is performed. Nitrogen diffuses from the MoN layer into the HfN layer in which nitrogen concentration is low and a work function is set by the HfN layer according to nitrogen concentration which depends on the nitrogen content of the HfN layer before the heat treatment and the amount of nitrogen that diffuses into the HfN layer. On the other hand, nitrogen hardly diffuses from the MoN layer into the HfN layer which originally has a certain nitrogen content, and a work function is set by the HfN layer according to nitrogen concentration in the HfN layer before the heat treatment. By controlling the nitrogen content of each layer and the amount of nitrogen that diffuses, a low-resistance metal gate electrode having a predetermined work function can be formed in each of the nMOS transistor formation region and the pMOS transistor formation region.
摘要翻译：可以制造具有各自具有适当功函数的具有低电阻金属栅电极的CMOS晶体管的半导体器件制造方法。形成其中nMOS晶体管形成区域中的氮浓度与pMOS晶体管形成区域中的氮浓度不同的HfN层。在HfN层上形成MoN层，进行热处理。氮从MoN层扩散到HfN层，其中氮浓度低，并且通过HfN层根据氮浓度设定功函数，氮浓度取决于热处理前的HfN层的氮含量和氮的量扩散到HfN层。另一方面，氮几乎从MoN层扩散到原来具有一定氮含量的HfN层中，并且通过HfN层根据HfN层中的氮浓度在热处理之前设定功函数。通过控制各层的氮含量和扩散的氮的量，可以在nMOS晶体管形成区域和pMOS晶体管形成区域中的每一个中形成具有预定功函数的低电阻金属栅电极。

4. 发明申请

US20100044799A1 METHOD FOR MANUFACTURING A P-TYPE MOS TRANSISTOR, METHOD FOR MANUFACTURING A CMOS-TYPE SEMICONDUCTOR APPARATUS HAVING THE P-TYPE MOS TRANSISTOR, AND CMOS-TYPE SEMICONDUCTOR APPARATUS MANUFACTURED USING THE MANUFACTURING METHOD 有权
标题翻译：用于制造P型MOS晶体管的方法，用于制造具有P型MOS晶体管的CMOS型半导体器件的方法，以及使用制造方法制造的CMOS型半导体器件
公开(公告)号：US20100044799A1
公开(公告)日：2010-02-25
申请号：US12541556
申请日：2009-08-14
申请人： Teruo Kurahashi , Yasuyoshi Mishima , Yukie Sakita
发明人： Teruo Kurahashi , Yasuyoshi Mishima , Yukie Sakita
IPC分类号： H01L27/092 , H01L21/28
CPC分类号： H01L21/823842 , H01L21/823835 , H01L29/4975 , H01L29/66545
摘要： A method for manufacturing a P-type MOS transistor includes forming a gate insulating film on the substrate, forming a gate electrode from amorphous silicon containing no impurities on the gate insulating film, performing a heat treatment for controlling the film characteristics of the amorphous silicon, depositing a nickel (Ni) layer on the gate electrode, and forming nickel silicides from the gate electrode and the nickel (Ni).
摘要翻译：一种P型MOS晶体管的制造方法，其特征在于，在所述基板上形成栅极绝缘膜，在所述栅极绝缘膜上形成不含有杂质的非晶硅的栅电极，进行用于控制所述非晶硅的膜特性的热处理，在栅电极上沉积镍（Ni）层，并从栅电极和镍（Ni）形成镍硅化物。

5. 发明授权

US08470653B2 Method for manufacturing a P-type MOS transistor, method for manufacturing a CMOS-type semiconductor apparatus having the P-type MOS transistor, and CMOS-type semiconductor apparatus manufactured using the manufacturing method 有权
标题翻译： P型MOS晶体管的制造方法，具有P型MOS晶体管的CMOS型半导体装置的制造方法以及使用该制造方法制造的CMOS型半导体装置
公开(公告)号：US08470653B2
公开(公告)日：2013-06-25
申请号：US12541556
申请日：2009-08-14
申请人： Teruo Kurahashi , Yasuyoshi Mishima , Yukie Sakita
发明人： Teruo Kurahashi , Yasuyoshi Mishima , Yukie Sakita
IPC分类号： H01L27/092
CPC分类号： H01L21/823842 , H01L21/823835 , H01L29/4975 , H01L29/66545
摘要： A method for manufacturing a P-type MOS transistor includes forming a gate insulating film on the substrate, forming a gate electrode from amorphous silicon containing no impurities on the gate insulating film, performing a heat treatment for controlling the film characteristics of the amorphous silicon, depositing a nickel (Ni) layer on the gate electrode, and forming nickel silicides from the gate electrode and the nickel (Ni).
摘要翻译：一种P型MOS晶体管的制造方法，其特征在于，在所述基板上形成栅极绝缘膜，在所述栅极绝缘膜上形成不含有杂质的非晶硅的栅电极，进行用于控制所述非晶硅的膜特性的热处理，在栅电极上沉积镍（Ni）层，并从栅电极和镍（Ni）形成镍硅化物。

6. 发明授权

US07968466B2 Fabrication process of a semiconductor device to form ultrafine patterns smaller than resolution limit of exposure apparatus 有权
标题翻译：半导体器件的制造工艺形成比曝光装置的分辨率极限小的超细图案
公开(公告)号：US07968466B2
公开(公告)日：2011-06-28
申请号：US11945547
申请日：2007-11-27
申请人： Kenji Ishikawa , Hideharu Shido , Takeo Nagata , Teruo Kurahashi , Yasuyoshi Mishima
发明人： Kenji Ishikawa , Hideharu Shido , Takeo Nagata , Teruo Kurahashi , Yasuyoshi Mishima
IPC分类号： H01L21/311
CPC分类号： H01L21/823456 , H01L21/823468 , H01L27/1057 , H01L27/10805 , H01L27/10873 , H01L27/11507
摘要： A method for fabricating an electron device on a substrate includes the steps of forming a dummy film over the substrate such that the dummy film covers a device region of the substrate and an outer region of the substrate outside the device region, forming a dummy pattern by patterning the dummy film such that the dummy pattern has a first height in the device region and a second height smaller than the first height in the outer region, forming another film over the substrate such that the film covers the dummy pattern in the device region and in the outer region with a shape conformal to a cross-sectional shape of the dummy pattern, and applying an anisotropic etching process acting generally perpendicularly to the substrate such that a surface of the substrate is exposed in the device region and in the outer region.
摘要翻译：一种在基板上制造电子器件的方法，包括以下步骤：在衬底上形成虚设膜，使得虚设膜覆盖衬底的器件区域和器件区域外的衬底的外部区域，通过图案化虚拟膜，使得虚设图案在器件区域中具有第一高度，并且第二高度小于外部区域中的第一高度，在衬底上形成另一膜，使得膜覆盖器件区域中的虚设图案，并且在外部区域具有与虚设图形的横截面形状一致的形状，以及施加大致垂直于基板的各向异性蚀刻工艺，使得基板的表面暴露在器件区域和外部区域中。

7. 发明授权

US07612400B2 MIM device and electronic apparatus 有权
标题翻译： MIM器件和电子设备
公开(公告)号：US07612400B2
公开(公告)日：2009-11-03
申请号：US11944847
申请日：2007-11-26
申请人： Teruo Kurahashi , Hideharu Shido , Kenji Ishikawa , Takeo Nagata , Yasuyoshi Mishima , Yukie Sakita
发明人： Teruo Kurahashi , Hideharu Shido , Kenji Ishikawa , Takeo Nagata , Yasuyoshi Mishima , Yukie Sakita
IPC分类号： H01L27/108
CPC分类号： H01L27/2472 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/1625
摘要： An MIM device includes a lower electrode of a metal nitride film, a hysteresis film of an oxide film containing Nb formed on the lower electrode, and an upper electrode of a metal nitride film formed on the hysteresis film.
摘要翻译： MIM器件包括金属氮化物膜的下电极，在下电极上形成含有Nb的氧化物膜的滞后膜和形成在滞后膜上的金属氮化物膜的上电极。

8. 发明申请

US20080124933A1 FABRICATION PROCESS OF A SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件的制造工艺
公开(公告)号：US20080124933A1
公开(公告)日：2008-05-29
申请号：US11945547
申请日：2007-11-27
申请人： Kenji Ishikawa , Hideharu Shido , Takeo Nagata , Teruo Kurahashi , Yasuyoshi Mishima
发明人： Kenji Ishikawa , Hideharu Shido , Takeo Nagata , Teruo Kurahashi , Yasuyoshi Mishima
IPC分类号： H01L21/8242 , H01L21/311
CPC分类号： H01L21/823456 , H01L21/823468 , H01L27/1057 , H01L27/10805 , H01L27/10873 , H01L27/11507
摘要： A method for fabricating an electron device on a substrate includes the steps of forming a dummy film over the substrate such that the dummy film covers a device region of the substrate and an outer region of the substrate outside the device region, forming a dummy pattern by patterning the dummy film such that the dummy patter has a first height in the device region and a second height smaller than the first height in the outer region, forming another film over the substrate such that the film covers the dummy pattern in the device region and in the outer region with a shape conformal to a cross-sectional shape of the dummy pattern, and applying an anisotropic etching process acting generally perpendicularly to the substrate such that a surface of the substrate is exposed in the device region and in the outer region.
摘要翻译：一种在基板上制造电子器件的方法，包括以下步骤：在衬底上形成虚设膜，使得虚设膜覆盖衬底的器件区域和器件区域外的衬底的外部区域，通过图案化虚拟膜，使得虚拟图案在器件区域中具有第一高度，并且第二高度小于外部区域中的第一高度，在衬底上形成另一膜，使得膜覆盖器件区域中的虚设图案，并且在外部区域具有与虚设图形的横截面形状一致的形状，以及施加大致垂直于基板的各向异性蚀刻工艺，使得基板的表面暴露在器件区域和外部区域中。

9. 发明申请

US20060208318A1 MOS field effect semiconductor device and method for fabricating the same 审中-公开
标题翻译： MOS场效应半导体器件及其制造方法
公开(公告)号：US20060208318A1
公开(公告)日：2006-09-21
申请号：US11370885
申请日：2006-03-09
申请人： Manabu Sakamoto , Teruo Kurahashi , Yasuyoshi Mishima
发明人： Manabu Sakamoto , Teruo Kurahashi , Yasuyoshi Mishima
IPC分类号： H01L29/78 , H01L21/8238
CPC分类号： H01L29/4966 , H01L21/28088 , H01L21/823842 , H01L29/66545 , H01L29/66583
摘要： A high-performance CMOS field effect semiconductor device using metal gate electrodes. An n-type gate electrode and a p-type gate electrode are formed by using a same metal and differ in nitrogen concentration. As a result, a high-performance CMOS field effect semiconductor device having the n-type gate electrode and the p-type gate electrode between which a work function difference is a predetermined value can be realized. By forming a low-resistance layer on layers which are formed by using the same metal and which differ in nitrogen concentration, it is possible to reduce the resistance of the n-type gate electrode and the p-type gate electrode while controlling the work functions of the n-type gate electrode and the p-type gate electrode. Therefore, a higher-performance CMOS field effect semiconductor device can be realized.
摘要翻译：一种使用金属栅电极的高性能CMOS场效应半导体器件。通过使用相同的金属形成n型栅电极和p型栅电极，氮浓度不同。结果，可以实现具有工作功能差为预定值的n型栅电极和p型栅电极的高性能CMOS场效应半导体器件。通过在通过使用相同的金属形成并且氮浓度不同的层上形成低电阻层，可以在控制工作功能的同时降低n型栅电极和p型栅电极的电阻的n型栅电极和p型栅电极。因此，可以实现更高性能的CMOS场效应半导体器件。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式