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1. 发明授权

US07001837B2 Semiconductor with tensile strained substrate and method of making the same 有权
标题翻译：具有拉伸应变衬底的半导体及其制造方法
公开(公告)号：US07001837B2
公开(公告)日：2006-02-21
申请号：US10346617
申请日：2003-01-17
申请人： Minh V. Ngo , Paul R. Besser , Ming Ren Lin , Haihong Wang
发明人： Minh V. Ngo , Paul R. Besser , Ming Ren Lin , Haihong Wang
IPC分类号： H01L21/4763
CPC分类号： H01L29/7843 , H01L29/1054 , H01L2924/0002 , Y10S257/90 , Y10S438/933 , H01L2924/00
摘要： An exemplary embodiment relates to a method for forming a metal oxide semiconductor field effect transistor (MOSFET). The method includes providing a substrate having a gate formed above the substrate and performing at least one of the following depositing steps: depositing a spacer layer and forming a spacer around a gate and gate insulator located above a layer of silicon above the substrate; depositing an etch stop layer above the spacer, the gate, and the layer of silicon; and depositing a dielectric layer above the etch stop layer. At least one of the depositing a spacer layer, depositing an etch stop layer, and depositing a dielectric layer comprises high compression deposition which increases in tensile strain in the layer of silicon.
摘要翻译：示例性实施例涉及形成金属氧化物半导体场效应晶体管（MOSFET）的方法。该方法包括提供一个衬底，该衬底具有形成在衬底上方的栅极，并且执行以下沉积步骤中的至少一个：在位于衬底上方的硅层上方的栅极和栅绝缘体周围沉积间隔层并形成间隔物; 在间隔物，栅极和硅层之上沉积蚀刻停止层; 以及在所述蚀刻停止层上沉积介电层。沉积间隔层，沉积蚀刻停止层和沉积介电层中的至少一个包括增加硅层中的拉伸应变的高压缩沉积。

2. 发明授权

US07701019B2 Tensile strained substrate 有权
标题翻译：拉伸应变基材
公开(公告)号：US07701019B2
公开(公告)日：2010-04-20
申请号：US11356606
申请日：2006-02-17
申请人： Minh V. Ngo , Paul R. Besser , Ming Ren Lin , Haihong Wang
发明人： Minh V. Ngo , Paul R. Besser , Ming Ren Lin , Haihong Wang
IPC分类号： H01L27/088
CPC分类号： H01L29/7843 , H01L29/1054 , H01L2924/0002 , Y10S257/90 , Y10S438/933 , H01L2924/00
摘要： An exemplary embodiment relates to a method for forming a metal oxide semiconductor field effect transistor (MOSFET). The method includes providing a substrate having a gate formed above the substrate and performing at least one of the following depositing steps: depositing a spacer layer and forming a spacer around a gate and gate insulator located above a layer of silicon above the substrate; depositing an etch stop layer above the spacer, the gate, and the layer of silicon; and depositing a dielectric layer above the etch stop layer. At least one of the depositing a spacer layer, depositing an etch stop layer, and depositing a dielectric layer comprises high compression deposition which increases in tensile strain in the layer of silicon.
摘要翻译：示例性实施例涉及形成金属氧化物半导体场效应晶体管（MOSFET）的方法。该方法包括提供一个衬底，该衬底具有形成在衬底上方的栅极，并且执行以下沉积步骤中的至少一个：在位于衬底上方的硅层上方的栅极和栅绝缘体周围沉积间隔层并形成间隔物; 在间隔物，栅极和硅层之上沉积蚀刻停止层; 以及在所述蚀刻停止层上沉积介电层。沉积间隔层，沉积蚀刻停止层和沉积介电层中的至少一个包括增加硅层中的拉伸应变的高压缩沉积。

3. 发明授权

US06924182B1 Strained silicon MOSFET having reduced leakage and method of its formation 有权
标题翻译：应变硅MOSFET具有减少的泄漏和其形成方法
公开(公告)号：US06924182B1
公开(公告)日：2005-08-02
申请号：US10642375
申请日：2003-08-15
申请人： Qi Xiang , Ming Ren Lin , Minh V. Ngo , Eric N. Paton , Haihong Wang
发明人： Qi Xiang , Ming Ren Lin , Minh V. Ngo , Eric N. Paton , Haihong Wang
IPC分类号： H01L21/762 , H01L21/8238 , H01L21/8234 , H01L21/76
CPC分类号： H01L21/823878 , H01L21/76237 , H01L21/823807
摘要： The formation of shallow trench isolations in a strained silicon MOSFET includes performing ion implantation in the strained silicon layer in the regions to be etched to form the trenches of the shallow trench isolations. The dosage of the implanted ions and the energy of implantation are chosen so as to damage the crystal lattice of the strained silicon throughout the thickness of the strained silicon layer in the shallow trench isolation regions to such a degree that the etch rate of the strained silicon in those regions is increased to approximately the same as or greater than the etch rate of the underlying undamaged silicon germanium. Subsequent etching yields trenches with significantly reduced or eliminated undercutting of the silicon germanium relative to the strained silicon. This in turn substantially prevents the formation of fully depleted silicon on insulator regions under the ends of the gate, thus improving the MOSFET leakage current.
摘要翻译：应变硅MOSFET中的浅沟槽隔离的形成包括在被蚀刻的区域中的应变硅层中执行离子注入以形成浅沟槽隔离的沟槽。选择注入离子的剂量和注入能量，以便在浅沟槽隔离区域中的应变硅层的整个厚度上损坏应变硅的晶格，使得应变硅的蚀刻速率在这些区域中增加到大致等于或大于底层未损坏的硅锗的蚀刻速率。随后的蚀刻产生相对于应变硅显着减少或消除硅锗底切的沟槽。这又大大防止了在栅极端部的绝缘体区域上形成完全耗尽的硅，从而改善MOSFET漏电流。

4. 发明授权

US06893929B1 Method of forming strained silicon MOSFET having improved threshold voltage under the gate ends 有权
标题翻译：形成栅极末端具有改善的阈值电压的应变硅MOSFET的方法
公开(公告)号：US06893929B1
公开(公告)日：2005-05-17
申请号：US10641548
申请日：2003-08-15
申请人： Qi Xiang , Ming Ren Lin , Minh V. Ngo , Haihong Wang
发明人： Qi Xiang , Ming Ren Lin , Minh V. Ngo , Haihong Wang
IPC分类号： H01L21/336 , H01L21/762 , H01L21/8234 , H01L29/10
CPC分类号： H01L29/6659 , H01L21/76237 , H01L21/823412 , H01L21/823481 , H01L29/1054 , H01L29/665 , H01L29/6656 , H01L29/7842 , Y10S438/933
摘要： The formation of shallow trench isolations in a strained silicon MOSFET includes implantation of a dopant into overhang portions of the strained silicon layer and silicon germanium layer at the edges of trenches in which shallow trench isolations are to be formed. The conductivity type of the dopant is chosen to be opposite the conductivity type of the source and drain dopants. The implanted dopant increases the threshold voltage Vt beneath the ends of the gate in overhang portions of the strained silicon layer so that it is approximately equal to or greater than that of the remainder of the MOSFET. The resulting strained silicon MOSFET exhibits reduced leakage current beneath the ends of the gate.
摘要翻译：应变硅MOSFET中浅沟槽隔离的形成包括将掺杂剂注入到将要形成浅沟槽隔离的沟槽边缘处的应变硅层和硅锗层的伸出部分。选择掺杂剂的导电类型与源极和漏极掺杂剂的导电类型相反。注入的掺杂剂在应变硅层的突出部分中增加栅极端部之下的阈值电压Vt，使得其大致等于或大于MOSFET的其余部分的阈值电压。所产生的应变硅MOSFET在栅极端部下方表现出减小的漏电流。

5. 发明授权

US06943087B1 Semiconductor on insulator MOSFET having strained silicon channel 有权
标题翻译：具有应变硅沟道的半导体绝缘体MOSFET
公开(公告)号：US06943087B1
公开(公告)日：2005-09-13
申请号：US10738529
申请日：2003-12-17
申请人： Qi Xiang , Jung-Suk Goo , James N. Pan , Ming Ren Lin
发明人： Qi Xiang , Jung-Suk Goo , James N. Pan , Ming Ren Lin
IPC分类号： H01L21/331 , H01L21/8222
CPC分类号： H01L29/66545 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L29/66772 , H01L29/7848 , H01L29/78654
摘要： Strained silicon is grown on a dielectric material in a trench in a silicon germanium layer at a channel region of a MOSFET after fabrication of other MOSFET elements using a removable dummy gate process to form an SOI MOSFET. The MOSFET is fabricated with the dummy gate in place, the dummy gate is removed, and a trench is formed in the channel region. Dielectric material is grown in the trench, and strained silicon is then grown from the silicon germanium trench sidewalls to form a strained silicon layer that extends across the dielectric material. The silicon germanium sidewalls impart strain to the strained silicon, and the presence of the dielectric material allows the strained silicon to be grown as a thin fully depleted layer. A replacement gate is then formed by damascene processing.
摘要翻译：在使用可移除的虚拟栅极工艺制造其它MOSFET元件以形成SOI MOSFET之后，将应变硅在MOSFET的沟道区的硅锗层中的沟槽中的电介质材料上生长。 MOSFET由虚拟栅极制造在位，虚拟栅极被去除，并且在沟道区域中形成沟槽。电介质材料在沟槽中生长，然后从硅锗沟槽侧壁生长应变硅，以形成延伸穿过电介质材料的应变硅层。硅锗侧壁对应变硅施加应变，并且电介质材料的存在允许应变硅作为薄的完全耗尽层生长。然后通过镶嵌加工形成替换浇口。

6. 发明授权

US06855982B1 Self aligned double gate transistor having a strained channel region and process therefor 有权
标题翻译：具有应变通道区域的自对准双栅极晶体管及其工艺
公开(公告)号：US06855982B1
公开(公告)日：2005-02-15
申请号：US10770163
申请日：2004-02-02
申请人： Qi Xiang , James N. Pan , Ming Ren Lin
发明人： Qi Xiang , James N. Pan , Ming Ren Lin
IPC分类号： H01L21/336 , H01L29/51 , H01L29/786 , H11L29/76
CPC分类号： H01L29/78696 , H01L29/51 , H01L29/518 , H01L29/66742 , H01L29/7842 , H01L29/78648 , H01L29/78684
摘要： A method of manufacturing an integrated circuit with a strained semiconductor channel region. The method can provide a double gate structure. The gate structure can be provided in and above a trench. The trench can be formed in a compound semiconductor material such as a silicon-germanium material. The strained semiconductor can increase the charge mobility associated with the transistor. A silicon-on-insulator substrate can be used.
摘要翻译：一种制造具有应变半导体沟道区域的集成电路的方法。该方法可以提供双栅结构。栅极结构可以设置在沟槽中和沟槽上方。沟槽可以形成在诸如硅 - 锗材料的化合物半导体材料中。应变半导体可以增加与晶体管相关的电荷迁移率。可以使用绝缘体上硅衬底。

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