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1. 发明授权

US07001840B1 Interconnect with multiple layers of conductive material with grain boundary between the layers 有权
标题翻译：与层之间具有晶界的多层导电材料互连
公开(公告)号：US07001840B1
公开(公告)日：2006-02-21
申请号：US10361332
申请日：2003-02-10
申请人： Minh Quoc Tran , Lu You , Fei Wang , Lynne Okada
发明人： Minh Quoc Tran , Lu You , Fei Wang , Lynne Okada
IPC分类号： H01L21/44
CPC分类号： H01L21/76879 , H01L21/2885
摘要： An interconnect structure is formed with a plurality of layers of a conductive material with a grain boundary between any two adjacent layers of the conductive material. Such grain boundaries between layers of conductive material act as shunt by-pass paths for migration of atoms of the conductive material to minimize migration of atoms of the conductive material along the interface between a dielectric passivation or capping layer and the interconnect structure. When the interconnect structure is a via structure, each of the layers of the conductive material and each of the grain boundary are formed to be perpendicular to a direction of current flow through the via structure. Such grain boundaries formed between the plurality of layers of conductive material in the via structure minimize charge carrier wind-force along the direction of current flow through the via structure to further minimize electromigration failure of the via structure.
摘要翻译：互连结构形成有导电材料的多层，在导电材料的任何两个相邻层之间具有晶界。导电材料层之间的这种晶界作为用于迁移导电材料的原子的分流旁通路径，以最小化导电材料原子沿着介电钝化层或覆盖层与互连结构之间的界面的迁移。当互连结构是通孔结构时，导电材料的每个层和每个晶界形成为垂直于通过过孔结构的电流的方向。在通孔结构中的多个导电材料层之间形成的这种晶界沿着通过通孔结构的电流流动的方向最小化载流子的风力，以进一步最小化通孔结构的电迁移故障。

2. 发明授权

US07256499B1 Ultra low dielectric constant integrated circuit system 有权
标题翻译：超低介电常数集成电路系统
公开(公告)号：US07256499B1
公开(公告)日：2007-08-14
申请号：US11230985
申请日：2005-09-19
申请人： Lu You , Fei Wang , Minh Quoc Tran , Lynne A. Okada
发明人： Lu You , Fei Wang , Minh Quoc Tran , Lynne A. Okada
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/5226 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit is provided including forming a porous ultra-low dielectric constant dielectric layer over a semiconductor substrate and forming an opening in the ultra-low dielectric constant dielectric layer. A dielectric liner is formed to line the opening to cover the pores in the ultra-low dielectric constant dielectric layer and a barrier layer is deposited to line the dielectric liner and conductor core is deposited to fill the opening over the barrier layer.
摘要翻译：提供了一种集成电路，包括在半导体衬底上形成多孔超低介电常数介电层，并在超低介电常数介电层中形成开口。形成电介质衬垫以使开口线对，以覆盖超低介电常数电介质层中的孔，并且沉积阻挡层以对电介质衬垫进行排列，并且沉积导体芯以填充阻挡层上的开口。

3. 发明授权

US07208418B1 Sealing sidewall pores in low-k dielectrics 有权
标题翻译：密封低k电介质中的侧壁孔
公开(公告)号：US07208418B1
公开(公告)日：2007-04-24
申请号：US10728774
申请日：2003-12-08
申请人： Lynne A. Okada , Minh Quoc Tran , Fei Wang , Lu You
发明人： Lynne A. Okada , Minh Quoc Tran , Fei Wang , Lu You
IPC分类号： H01L21/311
CPC分类号： H01L21/76831
摘要： Barrier metal layer discontinuities or gaps due to low-k dielectric porosity is reduced by sealing sidewall porosity before barrier metal layer deposition. Embodiments include sealing sidewall porosity by depositing a swelling agent, adhesion promoter or an additional layer of low-k material.
摘要翻译：通过在阻挡金属层沉积之前密封侧壁孔隙率来减少由于低k介电孔隙导致的阻挡金属层不连续性或间隙。实施例包括通过沉积溶胀剂，粘合促进剂或低k材料的附加层来密封侧壁孔隙。

4. 发明授权

US06756300B1 Method for forming dual damascene interconnect structure 有权
标题翻译：双镶嵌互连结构的形成方法
公开(公告)号：US06756300B1
公开(公告)日：2004-06-29
申请号：US10324259
申请日：2002-12-18
申请人： Fei Wang , Jerry Cheng , Lynne A. Okada , Minh Quoc Tran , Lu You
发明人： Fei Wang , Jerry Cheng , Lynne A. Okada , Minh Quoc Tran , Lu You
IPC分类号： H01L214763
CPC分类号： H01L21/76811 , H01L21/76813
摘要： For forming a dual damascene opening within a dielectric material, a via mask material and a trench mask material are formed over the dielectric material. A trench opening is formed through the trench mask material, and a via opening is formed through a via mask patterning material disposed over the via and trench mask materials. The via and trench mask materials exposed through the via opening of the via mask patterning material are etched away, and the via mask patterning material is etched away. A portion of the dielectric material exposed through the via opening is etched down to the underlying interconnect structure, and a portion of the dielectric material exposed through the trench opening is etched, to form the dual damascene opening.
摘要翻译：为了在介电材料内形成双镶嵌开口，在电介质材料上形成通孔掩模材料和沟槽掩模材料。通过沟槽掩模材料形成沟槽开口，并且通过布置在通孔和沟槽掩模材料上方的通孔掩模图案形成材料形成通孔开口。通过通孔掩模图形材料的通路孔露出的通孔和沟槽掩模材料被蚀刻掉，并且通孔掩模图案材料被蚀刻掉。通过通孔开口暴露的介电材料的一部分被蚀刻到下面的互连结构上，并且蚀刻通过沟槽开口露出的电介质材料的一部分，以形成双镶嵌开口。

5. 发明申请

US20090176369A1 LOW-H PLASMA TREATMENT WITH N2 ANNEAL FOR ELECTRONIC MEMORY DEVICES 有权
标题翻译：用于电子存储器件的N2天线的低等离子体处理
公开(公告)号：US20090176369A1
公开(公告)日：2009-07-09
申请号：US11971331
申请日：2008-01-09
申请人： Alexander H. Nickel , Allen L. Evans , Minh Quoc Tran , Lu You , Minh Van Ngo , Pei-Yuan Gao , William S. Brennan , Eric Wilson , Sung Jin Kim , Hieu Trung Pham
发明人： Alexander H. Nickel , Allen L. Evans , Minh Quoc Tran , Lu You , Minh Van Ngo , Pei-Yuan Gao , William S. Brennan , Eric Wilson , Sung Jin Kim , Hieu Trung Pham
IPC分类号： H01L21/44
CPC分类号： H01L21/76877 , H01L21/76814 , H01L21/76828 , H01L21/76834 , H01L21/76883 , Y10S438/902
摘要： A method for forming a single damascene and/or dual damascene, contact and interconnect structure, comprising: performing front end processing, depositing copper including a copper barrier, annealing the copper in at least 90% N2 with less than 10% H2, performing planarization, performing in-situ low-H NH3 plasma treatment and low Si—H SiN etch stop layer deposition, and performing remaining back end processing.
摘要翻译：一种用于形成单个镶嵌和/或双镶嵌，接触和互连结构的方法，包括：执行前端处理，沉积包含铜屏障的铜，在至少90％的N 2中以小于10％的H 2退火铜，进行平面化，进行原位低H NH 3等离子体处理和低Si-H SiN蚀刻停止层沉积，并执行剩余的后端处理。

6. 发明授权

US08202810B2 Low-H plasma treatment with N2 anneal for electronic memory devices 有权
标题翻译：用于电子存储器件的N 2退火的低-H等离子体处理
公开(公告)号：US08202810B2
公开(公告)日：2012-06-19
申请号：US11971331
申请日：2008-01-09
申请人： Alexander H. Nickel , Allen L. Evans , Minh Quoc Tran , Lu You , Minh Van Ngo , Pei-Yuan Gao , William S. Brennan , Erik Wilson , Sung Jin Kim , Hieu Trung Pham
发明人： Alexander H. Nickel , Allen L. Evans , Minh Quoc Tran , Lu You , Minh Van Ngo , Pei-Yuan Gao , William S. Brennan , Erik Wilson , Sung Jin Kim , Hieu Trung Pham
IPC分类号： H01L21/31
CPC分类号： H01L21/76877 , H01L21/76814 , H01L21/76828 , H01L21/76834 , H01L21/76883 , Y10S438/902
摘要： A method for forming a single damascene and/or dual damascene, contact and interconnect structure, comprising: performing front end processing, depositing copper including a copper barrier, annealing the copper in at least 90% N2 with less than 10% H2, performing planarization, performing in-situ low-H NH3 plasma treatment and low Si—H SiN etch stop layer deposition, and performing remaining back end processing.
摘要翻译：一种用于形成单个镶嵌和/或双镶嵌，接触和互连结构的方法，包括：执行前端处理，沉积包含铜屏障的铜，在至少90％的N 2中以小于10％的H 2退火铜，进行平面化，进行原位低H NH 3等离子体处理和低Si-H SiN蚀刻停止层沉积，并执行剩余的后端处理。

7. 发明授权

US06566248B1 Graphoepitaxial conductor cores in integrated circuit interconnects 有权
标题翻译：集成电路互连中的等顶导体芯
公开(公告)号：US06566248B1
公开(公告)日：2003-05-20
申请号：US09759114
申请日：2001-01-11
申请人： Pin-Chin Connie Wang , Minh Quoc Tran
发明人： Pin-Chin Connie Wang , Minh Quoc Tran
IPC分类号： H01L214763
CPC分类号： H01L21/76838 , H01L21/76877
摘要： A manufacturing method is provided for an integrated circuit having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening. A conductor core with a random grain texture fills the opening over the barrier layer. The crystallographic orientation of the conductor core is then graphoepitaxially changed to reduce its random grain texture.
摘要翻译：为具有半导体器件的半导体衬底的集成电路提供制造方法。在半导体衬底上形成器件电介质层。器件电介质层上的沟道电介质层具有形成在其中的开口。屏障层对通道开口进行排列。具有随机晶粒纹理的导体芯填充阻挡层上的开口。然后将导体芯的晶体取向作为薄膜表面改变以减少其随机晶粒纹理。

8. 发明授权

US06455413B1 Pre-fill CMP and electroplating method for integrated circuits 有权
标题翻译：集成电路制造方法，包括种子层的沉积，去除和随后的沉积
公开(公告)号：US06455413B1
公开(公告)日：2002-09-24
申请号：US09894525
申请日：2001-06-27
申请人： Christy Mei-Chu Woo , Minh Quoc Tran
发明人： Christy Mei-Chu Woo , Minh Quoc Tran
IPC分类号： H01L214763
CPC分类号： H01L21/76873 , H01L21/2885 , H01L21/7684 , H01L21/76843 , H01L21/76877 , H01L2221/1089
摘要： A manufacturing method for an integrated circuit is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening. A seed layer is deposited over the barrier layer. The seed and barrier layers are then removed above the channel dielectric layer. A second seed layer is deposited over the semiconductor substrate. A conductor layer is electroplated over the second seed layer to fill the opening. The electroplated conductor layer and the second seed layer are removed above the channel dielectric layer.
摘要翻译：提供了一种具有半导体器件的半导体衬底的集成电路的制造方法。在半导体衬底上形成器件电介质层。器件电介质层上的沟道电介质层具有形成在其中的开口。屏障层对通道开口进行排列。种子层沉积在阻挡层上。然后在通道介电层上方去除种子和阻挡层。第二晶种层沉积在半导体衬底上。导体层电镀在第二籽晶层上以填充开口。在沟道介电层上方去除电镀导体层和第二籽晶层。

9. 发明授权

US06583051B2 Method of manufacturing an amorphized barrier layer for integrated circuit interconnects 失效
公开(公告)号：US06583051B2
公开(公告)日：2003-06-24
申请号：US09989972
申请日：2001-11-20
申请人： Sergey D. Lopatin , Minh Van Ngo , Minh Quoc Tran
发明人： Sergey D. Lopatin , Minh Van Ngo , Minh Quoc Tran
IPC分类号： H01L214763
CPC分类号： H01L21/76843 , H01L21/76862 , H01L21/76873 , H01L23/53209 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： A manufacturing method for an integrated circuit is provided having a semiconductor substrate with a semiconductor device. A dielectric layer is on the semiconductor substrate and has an opening provided therein. An amorphized barrier layer lines the opening and a seed layer is deposited to line the amorphized barrier layer. A conductor core fills the opening over the barrier layer to form a conductor channel. The seed layer is securely bonded to the amorphized barrier layer and prevents electromigration along the surface between the seed and barrier layers.

10. 发明授权

US06541286B1 Imaging of integrated circuit interconnects 失效
标题翻译：集成电路互连成像
公开(公告)号：US06541286B1
公开(公告)日：2003-04-01
申请号：US09894284
申请日：2001-06-27
申请人： Joffre F. Bernard , Minh Quoc Tran
发明人： Joffre F. Bernard , Minh Quoc Tran
IPC分类号： G01R3126
CPC分类号： G01N23/043 , G01R31/302
摘要： A method is provided for X-ray imaging and analyzing grain boundaries, nodules or extrusions, voids, and separations or delaminations in conductive layers under dielectric capping layers in integrated circuit interconnects.
摘要翻译：提供了一种用于在集成电路互连中的介电覆盖层下的导电层中的X射线成像和分析晶界，结节或挤压，空隙以及分离或分层的方法。

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