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1. 发明授权

US07867848B2 Methods for fabricating dual bit flash memory devices 有权
标题翻译：制造双位闪存器件的方法
公开(公告)号：US07867848B2
公开(公告)日：2011-01-11
申请号：US12765646
申请日：2010-04-22
申请人： Minghao Shen , Fred Cheung , Ning Cheung , Wei Zheng , Hiroyuki Kinoshita , Chih-Yuh Yang
发明人： Minghao Shen , Fred Cheung , Ning Cheung , Wei Zheng , Hiroyuki Kinoshita , Chih-Yuh Yang
IPC分类号： H01L21/8239
CPC分类号： H01L27/11568 , H01L21/28282 , H01L29/7923
摘要： Methods for fabricating dual bit memory devices are provided. In an exemplary embodiment of the invention, a method for fabricating a dual bit memory device comprises forming a charge trapping layer overlying a substrate and etching an isolation opening through the charge trapping layer. An oxide layer is formed overlying the charge trapping layer and within the isolation opening. A control gate is fabricated overlying the isolation opening and portions of the charge trapping layer adjacent to the isolation opening. The oxide layer and the charge trapping layer are etched using the control gate as an etch mask and impurity dopants are implanted into the substrate using the control gate as an implantation mask.
摘要翻译：提供了制造双位存储器件的方法。在本发明的示例性实施例中，一种用于制造双位存储器件的方法包括形成覆盖衬底的电荷俘获层，并蚀刻穿过电荷俘获层的隔离开口。在电荷俘获层之上和隔离开口内形成氧化物层。制造控制栅极覆盖隔离开口和邻近隔离开口的电荷捕获层的部分。使用控制栅极作为蚀刻掩模蚀刻氧化物层和电荷俘获层，并且使用控制栅极作为注入掩模将杂质掺杂剂注入到衬底中。

2. 发明授权

US07732281B1 Methods for fabricating dual bit flash memory devices 有权
标题翻译：制造双位闪存器件的方法
公开(公告)号：US07732281B1
公开(公告)日：2010-06-08
申请号：US11410695
申请日：2006-04-24
申请人： Minghao Shen , Fred Cheung , Ning Cheng , Wei Zheng , Hiroyuki Kinoshita , Chih-Yuh Yang
发明人： Minghao Shen , Fred Cheung , Ning Cheng , Wei Zheng , Hiroyuki Kinoshita , Chih-Yuh Yang
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L21/28282 , H01L29/7923
摘要： Methods for fabricating dual bit memory devices are provided. In an exemplary embodiment of the invention, a method for fabricating a dual bit memory device comprises forming a charge trapping layer overlying a substrate and etching an isolation opening through the charge trapping layer. An oxide layer is formed overlying the charge trapping layer and within the isolation opening. A control gate is fabricated overlying the isolation opening and portions of the charge trapping layer adjacent to the isolation opening. The oxide layer and the charge trapping layer are etched using the control gate as an etch mask and impurity dopants are implanted into the substrate using the control gate as an implantation mask.
摘要翻译：提供了制造双位存储器件的方法。在本发明的示例性实施例中，一种用于制造双位存储器件的方法包括形成覆盖衬底的电荷俘获层，并蚀刻穿过电荷俘获层的隔离开口。在电荷俘获层之上和隔离开口内形成氧化物层。制造控制栅极覆盖隔离开口和邻近隔离开口的电荷捕获层的部分。使用控制栅极作为蚀刻掩模蚀刻氧化物层和电荷俘获层，并且使用控制栅极作为注入掩模将杂质掺杂剂注入到衬底中。

3. 发明申请

US20090039405A1 ORO AND ORPRO WITH BIT LINE TRENCH TO SUPPRESS TRANSPORT PROGRAM DISTURB 有权
标题翻译： ORO和ORPRO与位线TRENCH到禁止运输程序干扰
公开(公告)号：US20090039405A1
公开(公告)日：2009-02-12
申请号：US11835542
申请日：2007-08-08
申请人： Ning Cheng , K.T. Chang , Hiro Kinoshita , Chih-Yuh Yang , Lei Xue , Chungho Lee , Minghao Shen , Angela Hui , Huaqiang Wu
发明人： Ning Cheng , K.T. Chang , Hiro Kinoshita , Chih-Yuh Yang , Lei Xue , Chungho Lee , Minghao Shen , Angela Hui , Huaqiang Wu
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L27/115 , H01L21/28273 , H01L21/28282 , H01L27/11521 , H01L27/11568 , H01L29/42332 , H01L29/42348 , H01L29/66825 , H01L29/66833 , H01L29/7887 , H01L29/7923
摘要： Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line openings containing a bit line dielectric between the memory cells. The memory cell contains a charge storage layer and a first poly gate. The bit line opening extends into the semiconductor substrate. By containing the bit line dielectric in the bit line openings that extend into the semiconductor substrate, the memory device can improve the electrical isolation between memory cells, thereby preventing and/or mitigating TPD.
摘要翻译：提供了具有改善的TPD特性的存储器件和制造存储器件的方法。存储器件在半导体衬底上包含两个或更多个存储单元，并且在存储单元之间包含位线电介质的位线开口。存储单元包含电荷存储层和第一多晶硅栅极。位线开口延伸到半导体衬底中。通过将延伸到半导体衬底的位线开口中的位线电介质包含在内，存储器件可以改善存储器单元之间的电隔离，从而防止和/或减轻TPD。

4. 发明授权

US09245895B2 Oro and orpro with bit line trench to suppress transport program disturb 有权
标题翻译： Oro和orpro与位线沟槽抑制传输程序干扰
公开(公告)号：US09245895B2
公开(公告)日：2016-01-26
申请号：US13190565
申请日：2011-07-26
申请人： Ning Cheng , Kuo-Tung Chang , Hiro Kinoshita , Chih-Yuh Yang , Lei Xue , Chungho Lee , Minghao Shen , Angela Hui , Huaqiang Wu
发明人： Ning Cheng , Kuo-Tung Chang , Hiro Kinoshita , Chih-Yuh Yang , Lei Xue , Chungho Lee , Minghao Shen , Angela Hui , Huaqiang Wu
IPC分类号： H01L29/788 , H01L27/115 , H01L21/28 , H01L29/423 , H01L29/66 , H01L29/792
CPC分类号： H01L27/115 , H01L21/28273 , H01L21/28282 , H01L27/11521 , H01L27/11568 , H01L29/42332 , H01L29/42348 , H01L29/66825 , H01L29/66833 , H01L29/7887 , H01L29/7923
摘要： Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line openings containing a bit line dielectric between the memory cells. The memory cell contains a charge storage layer and a first poly gate. The bit line opening extends into the semiconductor substrate. By containing the bit line dielectric in the bit line openings that extend into the semiconductor substrate, the memory device can improve the electrical isolation between memory cells, thereby preventing and/or mitigating TPD.
摘要翻译：提供了具有改善的TPD特性的存储器件和制造存储器件的方法。存储器件在半导体衬底上包含两个或更多个存储单元，并且在存储单元之间包含位线电介质的位线开口。存储单元包含电荷存储层和第一多晶硅栅极。位线开口延伸到半导体衬底中。通过将延伸到半导体衬底的位线开口中的位线电介质包含在内，存储器件可以改善存储器单元之间的电隔离，从而防止和/或减轻TPD。

5. 发明申请

US20110278660A1 ORO AND ORPRO WITH BIT LINE TRENCH TO SUPPRESS TRANSPORT PROGRAM DISTURB 有权
标题翻译： ORO和ORPRO与位线TRENCH到禁止运输程序干扰
公开(公告)号：US20110278660A1
公开(公告)日：2011-11-17
申请号：US13190565
申请日：2011-07-26
申请人： Ning Cheng , K.T. Chang , Hiro Kinoshita , Chih-Yuh Yang , Lei Xue , Chungho Lee , Minghao Shen , Angela Hui , Huaqiang Wu
发明人： Ning Cheng , K.T. Chang , Hiro Kinoshita , Chih-Yuh Yang , Lei Xue , Chungho Lee , Minghao Shen , Angela Hui , Huaqiang Wu
IPC分类号： H01L29/792
CPC分类号： H01L27/115 , H01L21/28273 , H01L21/28282 , H01L27/11521 , H01L27/11568 , H01L29/42332 , H01L29/42348 , H01L29/66825 , H01L29/66833 , H01L29/7887 , H01L29/7923
摘要： Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line openings containing a bit line dielectric between the memory cells. The memory cell contains a charge storage layer and a first poly gate. The bit line opening extends into the semiconductor substrate. By containing the bit line dielectric in the bit line openings that extend into the semiconductor substrate, the memory device can improve the electrical isolation between memory cells, thereby preventing and/or mitigating TPD.
摘要翻译：提供了具有改善的TPD特性的存储器件和制造存储器件的方法。存储器件在半导体衬底上包含两个或更多个存储单元，并且在存储单元之间包含位线电介质的位线开口。存储单元包含电荷存储层和第一多晶硅栅极。位线开口延伸到半导体衬底中。通过将延伸到半导体衬底的位线开口中的位线电介质包含在内，存储器件可以改善存储器单元之间的电隔离，从而防止和/或减轻TPD。

6. 发明授权

US08012830B2 ORO and ORPRO with bit line trench to suppress transport program disturb 有权
标题翻译： ORO和ORPRO与位线沟槽抑制传输程序干扰
公开(公告)号：US08012830B2
公开(公告)日：2011-09-06
申请号：US11835542
申请日：2007-08-08
申请人： Ning Cheng , Kuo-Tung Chang , Hiro Kinoshita , Chih-Yuh Yang , Lei Xue , Chungho Lee , Minghao Shen , Angela Hui , Huaqiang Wu
发明人： Ning Cheng , Kuo-Tung Chang , Hiro Kinoshita , Chih-Yuh Yang , Lei Xue , Chungho Lee , Minghao Shen , Angela Hui , Huaqiang Wu
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L21/28273 , H01L21/28282 , H01L27/11521 , H01L27/11568 , H01L29/42332 , H01L29/42348 , H01L29/66825 , H01L29/66833 , H01L29/7887 , H01L29/7923
摘要： Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line openings containing a bit line dielectric between the memory cells. The memory cell contains a charge storage layer and a first poly gate. The bit line opening extends into the semiconductor substrate. By containing the bit line dielectric in the bit line openings that extend into the semiconductor substrate, the memory device can improve the electrical isolation between memory cells, thereby preventing and/or mitigating TPD.
摘要翻译：提供了具有改善的TPD特性的存储器件和制造存储器件的方法。存储器件在半导体衬底上包含两个或更多个存储单元，并且在存储单元之间包含位线电介质的位线开口。存储单元包含电荷存储层和第一多晶硅栅极。位线开口延伸到半导体衬底中。通过将延伸到半导体衬底的位线开口中的位线电介质包含在内，存储器件可以改善存储器单元之间的电隔离，从而防止和/或减轻TPD。

7. 发明授权

US07829936B2 Split charge storage node inner spacer process 有权
标题翻译：分离电荷存储节点内隔离过程
公开(公告)号：US07829936B2
公开(公告)日：2010-11-09
申请号：US11873822
申请日：2007-10-17
申请人： Minghao Shen , Shenqing Fang , Wai Lo , Christie R. K. Marrian , Chungho Lee , Ning Cheng , Fred Cheung , Huaqiang Wu
发明人： Minghao Shen , Shenqing Fang , Wai Lo , Christie R. K. Marrian , Chungho Lee , Ning Cheng , Fred Cheung , Huaqiang Wu
IPC分类号： H01L21/331
CPC分类号： H01L29/7923 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/42344
摘要： Methods of forming a memory cell containing two split sub-lithographic charge storage nodes on a semiconductor substrate are provided. The methods can involve forming two split sub-lithographic charge storage nodes by using spacer formation techniques. By removing exposed portions of a first poly layer while leaving portions of the first poly layer protected by the spacers, the method can provide two split sub-lithographic first poly gates. Further, by removing exposed portions of a charge storage layer while leaving portions of the charge storage layer protected by the two split sub-lithographic first poly gates, the method can provide two split, narrow portions of the charge storage layer, which subsequently form two split sub-lithographic charge storage nodes.
摘要翻译：提供了在半导体衬底上形成包含两个分开的次光刻电荷存储节点的存储单元的方法。这些方法可以包括通过使用间隔物形成技术形成两个分裂的亚光刻电荷存储节点。通过去除第一多晶硅层的暴露部分，同时留下被间隔物保护的第一多晶硅层的部分，该方法可以提供两个分裂的次光刻的第一多晶硅栅极。此外，通过去除电荷存储层的暴露部分，同时保留由两个分割子光刻第一多晶硅栅极保护的电荷存储层的部分，该方法可以提供电荷存储层的两个分开的窄部分，其随后形成两个拆分次光刻电荷存储节点。

8. 发明申请

US20090101963A1 SPLIT CHARGE STORAGE NODE INNER SPACER PROCESS 有权
标题翻译：分离式充电储存装置内部空间过程
公开(公告)号：US20090101963A1
公开(公告)日：2009-04-23
申请号：US11873822
申请日：2007-10-17
申请人： Minghao Shen , Shenqing Fang , Wai Lo , Christie R.K. Marrian , Chungho Lee , Ning Cheng , Fred Cheung , Huaqiang Wu
发明人： Minghao Shen , Shenqing Fang , Wai Lo , Christie R.K. Marrian , Chungho Lee , Ning Cheng , Fred Cheung , Huaqiang Wu
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/7923 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/42344
摘要： Methods of forming a memory cell containing two split sub-lithographic charge storage nodes on a semiconductor substrate are provided. The methods can involve forming two split sub-lithographic charge storage nodes by using spacer formation techniques. By removing exposed portions of a first poly layer while leaving portions of the first poly layer protected by the spacers, the method can provide two split sub-lithographic first poly gates. Further, by removing exposed portions of a charge storage layer while leaving portions of the charge storage layer protected by the two split sub-lithographic first poly gates, the method can provide two split, narrow portions of the charge storage layer, which subsequently form two split sub-lithographic charge storage nodes.
摘要翻译：提供了在半导体衬底上形成包含两个分开的次光刻电荷存储节点的存储单元的方法。这些方法可以包括通过使用间隔物形成技术形成两个分裂的亚光刻电荷存储节点。通过去除第一多晶硅层的暴露部分，同时留下被间隔物保护的第一多晶硅层的部分，该方法可以提供两个分裂的次光刻的第一多晶硅栅极。此外，通过去除电荷存储层的暴露部分，同时保留由两个分割子光刻第一多晶硅栅极保护的电荷存储层的部分，该方法可以提供电荷存储层的两个分开的窄部分，其随后形成两个拆分次光刻电荷存储节点。

9. 发明授权

US09224748B2 Method of forming spaced-apart charge trapping stacks 有权
标题翻译：形成间隔开的电荷捕获堆叠的方法
公开(公告)号：US09224748B2
公开(公告)日：2015-12-29
申请号：US12696409
申请日：2010-01-29
申请人： Hiroyuki Kinoshita , Ning Cheng , Minghao Shen
发明人： Hiroyuki Kinoshita , Ning Cheng , Minghao Shen
IPC分类号： H01L27/115
CPC分类号： H01L27/11563 , H01L27/115 , H01L27/11568
摘要： Methods are provided for fabricating memory devices. A method comprises fabricating charge-trapping stacks overlying a silicon substrate and forming bit line regions in the substrate between the charge trapping stacks. Insulating elements are formed overlying the bit line regions between the stacks. The charge-trapping stacks are etched to form two complementary charge storage nodes and to expose portions of the silicon substrate. Silicon is grown on the exposed silicon substrate by selective epitaxial growth and is oxidized. A control gate layer is formed overlying the complementary charge storage nodes and the oxidized epitaxially-grown silicon.
摘要翻译：提供了用于制造存储器件的方法。一种方法包括制造覆盖在硅衬底上的电荷俘获堆叠，并在电荷俘获堆叠之间形成衬底中的位线区域。绝缘元件形成在堆叠之间的位线区域之上。电荷俘获堆被蚀刻以形成两个互补电荷存储节点并暴露硅衬底的部分。硅通过选择性外延生长在暴露的硅衬底上生长并被氧化。形成覆盖互补电荷存储节点和氧化的外延生长硅的控制栅层。

10. 发明申请

US20090108330A1 SPLIT CHARGE STORAGE NODE OUTER SPACER PROCESS 有权
标题翻译：分离式充电储存节点外部间隔过程
公开(公告)号：US20090108330A1
公开(公告)日：2009-04-30
申请号：US11924169
申请日：2007-10-25
申请人： Minghao Shen , Chungho Lee , Hiroyuki Kinoshita , Huaqiang Wu
发明人： Minghao Shen , Chungho Lee , Hiroyuki Kinoshita , Huaqiang Wu
IPC分类号： H01L29/792 , H01L21/3205
CPC分类号： H01L29/7923 , H01L21/0337 , H01L21/0338 , H01L21/32139 , H01L27/115 , H01L27/11568
摘要： Memory cells containing two split sub-lithographic charge storage nodes on a semiconductor substrate and methods for making the memory cells are provided. The methods can involve forming two split sub-lithographic charge storage nodes by using spacer formation techniques. By removing an exposed portion of a fist poly layer between sloping side surfaces or outer surfaces of spacers while leaving portions of the first poly layer protected by the spacers, the method can provide two split sub-lithographic first poly gates. Further, by removing an exposed portion of a charge storage layer between sloping side surfaces or outer surfaces of spacers, the method can provide two split, narrow portions of the charge storage layer, which subsequently form two split sub-lithographic charge storage nodes.
摘要翻译：提供了包含半导体衬底上的两个分裂子光刻电荷存储节点的存储单元以及用于制造存储单元的方法。这些方法可以包括通过使用间隔物形成技术形成两个分裂的亚光刻电荷存储节点。通过在间隔物的倾斜侧表面或外表面之间除去第一多晶硅层的暴露部分，同时留下被间隔物保护的第一多晶硅层的部分，该方法可以提供两个分裂的次光刻的第一多晶硅栅极。此外，通过去除间隔物的倾斜侧表面或外表面之间的电荷存储层的暴露部分，该方法可以提供电荷存储层的两个分开的窄部分，其随后形成两个分裂的亚光刻电荷存储节点。

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