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1. 发明授权

US06800910B2 FinFET device incorporating strained silicon in the channel region 有权
标题翻译： FinFET器件在通道区域中包含应变硅
公开(公告)号：US06800910B2
公开(公告)日：2004-10-05
申请号：US10335474
申请日：2002-12-31
申请人： Ming-Ren Lin , Jung-Suk Goo , Haihong Wang , Qi Xiang
发明人： Ming-Ren Lin , Jung-Suk Goo , Haihong Wang , Qi Xiang
IPC分类号： H01L27105
CPC分类号： H01L29/785 , H01L29/1054 , H01L29/42384 , H01L29/66795 , H01L29/78603 , H01L29/78687
摘要： A FinFET device employs strained silicon to enhance carrier mobility. In one method, a FinFET body is patterned from a layer of silicon germanium (SiGe) that overlies a dielectric layer. An epitaxial layer of silicon is then formed on the silicon germanium FinFET body. A strain is induced in the epitaxial silicon as a result of the different dimensionalities of intrinsic silicon and of the silicon germanium crystal lattice that serves as the template on which the epitaxial silicon is grown. Strained silicon has an increased carrier mobility compared to relaxed silicon, and as a result the epitaxial strained silicon provides increased carrier mobility in the FinFET. A higher driving current can therefore be realized in a FinFET employing a strained silicon channel layer.
摘要翻译： FinFET器件采用应变硅来增强载流子迁移率。在一种方法中，FinFET体从覆盖在电介质层上的硅锗层（SiGe）构图。然后在硅锗FinFET体上形成硅的外延层。由于本征硅和作为外延硅生长的模板的硅锗晶格的不同维度，在外延硅中引起应变。与松弛硅相比，应变硅具有增加的载流子迁移率，结果外延应变硅在FinFET中提供增加的载流子迁移率。因此，可以在采用应变硅沟道层的FinFET中实现更高的驱动电流。

2. 发明授权

US06962857B1 Shallow trench isolation process using oxide deposition and anneal 有权
标题翻译：使用氧化物沉积和退火的浅沟槽隔离工艺
公开(公告)号：US06962857B1
公开(公告)日：2005-11-08
申请号：US10358966
申请日：2003-02-05
申请人： Minh-Van Ngo , Ming-Ren Lin , Eric N. Paton , Haihong Wang , Qi Xiang , Jung-Suk Goo
发明人： Minh-Van Ngo , Ming-Ren Lin , Eric N. Paton , Haihong Wang , Qi Xiang , Jung-Suk Goo
IPC分类号： H01L21/76 , H01L21/762 , H01L21/8234 , H01L21/8238
CPC分类号： H01L21/76224 , H01L21/823412 , H01L21/823481 , H01L21/823807 , H01L21/823878
摘要： A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in a strained silicon (SMOS) process. The liner for the trench is formed from a layer deposited in a low temperature process which reduces germanium outgassing. The low temperature process can be an LPCVD. An annealing step can be utilized to form the liner.
摘要翻译：集成电路（IC）的制造方法利用浅沟槽隔离（STI）技术。浅沟槽隔离技术用于应变硅（SMOS）工艺。用于沟槽的衬垫由沉积在低温过程中的层形成，其减少锗除气。低温过程可以是LPCVD。可以使用退火步骤来形成衬垫。

3. 发明授权

US06943087B1 Semiconductor on insulator MOSFET having strained silicon channel 有权
标题翻译：具有应变硅沟道的半导体绝缘体MOSFET
公开(公告)号：US06943087B1
公开(公告)日：2005-09-13
申请号：US10738529
申请日：2003-12-17
申请人： Qi Xiang , Jung-Suk Goo , James N. Pan , Ming Ren Lin
发明人： Qi Xiang , Jung-Suk Goo , James N. Pan , Ming Ren Lin
IPC分类号： H01L21/331 , H01L21/8222
CPC分类号： H01L29/66545 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L29/66772 , H01L29/7848 , H01L29/78654
摘要： Strained silicon is grown on a dielectric material in a trench in a silicon germanium layer at a channel region of a MOSFET after fabrication of other MOSFET elements using a removable dummy gate process to form an SOI MOSFET. The MOSFET is fabricated with the dummy gate in place, the dummy gate is removed, and a trench is formed in the channel region. Dielectric material is grown in the trench, and strained silicon is then grown from the silicon germanium trench sidewalls to form a strained silicon layer that extends across the dielectric material. The silicon germanium sidewalls impart strain to the strained silicon, and the presence of the dielectric material allows the strained silicon to be grown as a thin fully depleted layer. A replacement gate is then formed by damascene processing.
摘要翻译：在使用可移除的虚拟栅极工艺制造其它MOSFET元件以形成SOI MOSFET之后，将应变硅在MOSFET的沟道区的硅锗层中的沟槽中的电介质材料上生长。 MOSFET由虚拟栅极制造在位，虚拟栅极被去除，并且在沟道区域中形成沟槽。电介质材料在沟槽中生长，然后从硅锗沟槽侧壁生长应变硅，以形成延伸穿过电介质材料的应变硅层。硅锗侧壁对应变硅施加应变，并且电介质材料的存在允许应变硅作为薄的完全耗尽层生长。然后通过镶嵌加工形成替换浇口。

4. 发明授权

US06858503B1 Depletion to avoid cross contamination 失效
标题翻译：消耗以避免交叉污染
公开(公告)号：US06858503B1
公开(公告)日：2005-02-22
申请号：US10358484
申请日：2003-02-05
申请人： Minh V. Ngo , Ming-Ren Lin , Paul R. Besser , Qi Xiang , Eric N. Paton , Jung-Suk Goo
发明人： Minh V. Ngo , Ming-Ren Lin , Paul R. Besser , Qi Xiang , Eric N. Paton , Jung-Suk Goo
IPC分类号： H01L21/306 , H01L29/10 , H01L21/336
CPC分类号： H01L21/02046 , H01L29/1054
摘要： A fabrication system utilizes a protocol for removing germanium from a top surface of a wafer. An exposure to a gas, such as a gas containing the hydrochloric acid can remove germanium from the top surface. The protocol can allow shared equipment to be used in both Flash product fabrication lines and strained silicon (SMOS) fabrication lines. The protocol allows better silicidation in SMOS devices.
摘要翻译：制造系统利用从晶片顶表面去除锗的方案。暴露于气体，如含有盐酸的气体，可以从上表面除去锗。该协议可以允许在Flash产品制造线和应变硅（SMOS）生产线中使用共享设备。该协议允许在SMOS器件中更好的硅化。

5. 发明授权

US06730576B1 Method of forming a thick strained silicon layer and semiconductor structures incorporating a thick strained silicon layer 有权
标题翻译：形成厚应变硅层的方法和掺入厚应变硅层的半导体结构
公开(公告)号：US06730576B1
公开(公告)日：2004-05-04
申请号：US10335447
申请日：2002-12-31
申请人： Haihong Wang , Paul R. Besser , Jung-Suk Goo , Minh V. Ngo , Eric N. Paton , Qi Xiang
发明人： Haihong Wang , Paul R. Besser , Jung-Suk Goo , Minh V. Ngo , Eric N. Paton , Qi Xiang
IPC分类号： H01L21762
CPC分类号： H01L29/7833 , H01L21/02381 , H01L21/0245 , H01L21/0251 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/76224 , H01L29/1054 , H01L29/665 , H01L29/6656 , H01L29/6659
摘要： A strained silicon layer is grown on a layer of silicon germanium and a layer of silicon germanium is grown on the strained silicon in a single continuous in situ deposition process with the strained silicon. Shallow trench isolations are formed in the lower layer of silicon germanium prior to formation of the strained silicon layer. The two silicon germanium layers effectively provide dual substrates at both surfaces of the strained silicon layer that serve to maintain the tensile strain of the strained silicon layer and resist the formation of misfit dislocations that might otherwise result from temperature changes during processing. Consequently the critical thickness of strained silicon that can be grown without significant misfit dislocations during later processing is effectively doubled for a given germanium content of the silicon germanium layers. The formation of shallow trench isolations prior to formation of the strained silicon layer avoids subjecting the strained silicon layer to extreme thermal stresses and further reduces the formation of misfit dislocations.
摘要翻译：应变硅层在硅锗层上生长，并且在应变硅上生长硅锗层，并在应变硅中进行单次连续原位沉积工艺。在形成应变硅层之前，在硅锗的下层形成浅沟槽隔离。两个硅锗层有效地在应变硅层的两个表面上提供双重衬底，其用于维持应变硅层的拉伸应变，并抵抗由加工过程中的温度变化引起的失配位错的形成。因此，对于硅锗层的给定锗含量，可以在后续处理期间可以生长而不显着失配位错的应变硅的临界厚度被有效地加倍。在形成应变硅层之前形成浅沟槽隔离避免使应变硅层受到极端的热应力，并进一步减少失配位错的形成。

6. 发明授权

US07170084B1 Strained silicon MOSFET having improved source/drain extension dopant diffusion resistance and method for its fabrication 有权
标题翻译：具有改善的源极/漏极延伸掺杂剂扩散电阻的应变硅MOSFET及其制造方法
公开(公告)号：US07170084B1
公开(公告)日：2007-01-30
申请号：US10872707
申请日：2004-06-21
申请人： Qi Xiang , Jung-Suk Goo , Haihong Wang
发明人： Qi Xiang , Jung-Suk Goo , Haihong Wang
IPC分类号： H01L29/06 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： H01L29/66477 , H01L21/26586 , H01L29/1045 , H01L29/1054 , H01L29/665
摘要： An n-type MOSFET (NMOS) is implemented on a substrate having an epitaxial layer of strained silicon formed on a layer of silicon germanium. The MOSFET includes first halo regions formed in the strained silicon layer that extent toward the channel region beyond the ends of shallow source and drain extensions. Second halo regions formed in the underlying silicon germanium layer extend toward the channel region beyond the ends of the shallow source and drain extensions and extend deeper into the silicon germanium layer than the shallow source and drain extensions. The p-type dopant of the first and second halo regions slows the high rate of diffusion of the n-type dopant of the shallow source and drain extensions through the silicon germanium toward the channel region. By counteracting the increased diffusion rate of the n-type dopant in this manner, the shallow source and drain extension profiles are maintained and the risk of degradation by short channel effects is reduced.
摘要翻译：在具有形成在硅锗层上的应变硅的外延层的衬底上实施n型MOSFET（NMOS）。 MOSFET包括形成在应变硅层中的第一晕圈，其范围朝向超过浅源极和漏极延伸端的沟道区域。形成在下面的硅锗层中的第二晕圈延伸到超过浅源极和漏极延伸端的沟道区，并且比浅源极和漏极延伸部更深地延伸到硅锗层中。第一和第二晕圈区域的p型掺杂剂减缓了浅源极和漏极延伸部分的n型掺杂剂通过硅锗朝向沟道区的高扩散速率。通过以这种方式抵消增加的n型掺杂剂的扩散速率，维持浅的源极和漏极延伸分布，并且降低由短沟道效应引起的退化的风险。

7. 发明授权

US06902991B2 Semiconductor device having a thick strained silicon layer and method of its formation 有权
标题翻译：具有厚的应变硅层的半导体器件及其形成方法
公开(公告)号：US06902991B2
公开(公告)日：2005-06-07
申请号：US10282513
申请日：2002-10-24
申请人： Qi Xiang , Jung-Suk Goo , Haihong Wang
发明人： Qi Xiang , Jung-Suk Goo , Haihong Wang
IPC分类号： H01L21/20 , H01L21/205 , H01L21/336 , H01L21/337 , H01L29/10 , H01L21/04
CPC分类号： H01L29/1054 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L21/02636 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66795 , H01L29/66893
摘要： A strained silicon layer is grown on a layer of silicon germanium and a second layer of silicon germanium is grown on the layer of strained silicon in a single continuous in situ deposition process. Both layers of silicon germanium may be grown in situ with the strained silicon. This construction effectively provides dual substrates at both sides of the strained silicon layer to support the tensile strain of the strained silicon layer and to resist the formation of misfit dislocations that may be induced by temperature changes during processing. Consequently the critical thickness of strained silicon that can be grown on substrates having a given germanium content is effectively doubled. The silicon germanium layer overlying the strained silicon layer may be maintained during MOSFET processing to resist creation of misfit dislocations in the strained silicon layer up to the time of formation of gate insulating material.
摘要翻译：在硅锗层上生长应变硅层，并且在单个连续原位沉积工艺中，在应变硅层上生长第二层硅锗。硅锗的两层可以用应变硅原位生长。这种结构在应变硅层的两侧有效地提供了两个基板，以支撑应变硅层的拉伸应变，并且抵抗可能在加工过程中温度变化引起的失配位错的形成。因此，可以在具有给定锗含量的衬底上生长的应变硅的临界厚度被有效地加倍。覆盖应变硅层的硅锗层可以在MOSFET加工过程中保持，以抵抗在形成栅极绝缘材料时产生应变硅层中的失配位错。

8. 发明授权

US06756276B1 Strained silicon MOSFET having improved source/drain extension dopant diffusion resistance and method for its fabrication 有权
标题翻译：具有改善的源极/漏极延伸掺杂剂扩散电阻的应变硅MOSFET及其制造方法
公开(公告)号：US06756276B1
公开(公告)日：2004-06-29
申请号：US10335522
申请日：2002-12-31
申请人： Qi Xiang , Jung-Suk Goo , Haihong Wang
发明人： Qi Xiang , Jung-Suk Goo , Haihong Wang
IPC分类号： H01L21336
CPC分类号： H01L29/66477 , H01L21/26586 , H01L29/1045 , H01L29/1054 , H01L29/665
摘要： An n-type MOSFET (NMOS) is implemented on a substrate having an epitaxial layer of strained silicon formed on a layer of silicon germanium. The MOSFET includes first halo regions formed in the strained silicon layer that extent toward the channel region beyond the ends of shallow source and drain extensions. Second halo regions formed in the underlying silicon germanium layer extend toward the channel region beyond the ends of the shallow source and drain extensions and extend deeper into the silicon germanium layer than the shallow source and drain extensions. The p-type dopant of the first and second halo regions slows the high rate of diffusion of the n-type dopant of the shallow source and drain extensions through the silicon germanium toward the channel region. By counteracting the increased diffusion rate of the n-type dopant in this manner, the shallow source and drain extension profiles are maintained and the risk of degradation by short channel effects is reduced.
摘要翻译：在具有形成在硅锗层上的应变硅的外延层的衬底上实施n型MOSFET（NMOS）。 MOSFET包括形成在应变硅层中的第一晕圈，其范围朝向超过浅源极和漏极延伸端的沟道区域。形成在下面的硅锗层中的第二晕圈延伸到超过浅源极和漏极延伸端的沟道区，并且比浅源极和漏极延伸部更深地延伸到硅锗层中。第一和第二晕圈区域的p型掺杂剂减缓了浅源极和漏极延伸部分的n型掺杂剂通过硅锗朝向沟道区的高扩散速率。通过以这种方式抵消增加的n型掺杂剂的扩散速率，维持浅的源极和漏极延伸分布，并且降低由短沟道效应引起的退化的风险。

9. 发明申请

US20090047770A1 METHOD OF FORMING ISOLATION REGIONS FOR INTEGRATED CIRCUITS 有权
标题翻译：形成集成电路隔离区的方法
公开(公告)号：US20090047770A1
公开(公告)日：2009-02-19
申请号：US12205361
申请日：2008-09-05
申请人： Haihong Wang , Minh-Van Ngo , Qi Xiang , Paul R. Besser , Eric N. Paton , Ming-Ren Lin
发明人： Haihong Wang , Minh-Van Ngo , Qi Xiang , Paul R. Besser , Eric N. Paton , Ming-Ren Lin
IPC分类号： H01L21/76
CPC分类号： H01L21/76224 , H01L21/823481 , H01L29/1054
摘要： A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed from a semiconductor or metal layer which is deposited in a low temperature process which reduces germanium outgassing. The low temperature process can be a ALD process.
摘要翻译：集成电路（IC）的制造方法利用浅沟槽隔离（STI）技术。浅沟槽隔离技术用于应变硅（SMOS）工艺。用于沟槽的衬垫由半导体或金属层形成，该半导体或金属层在低温过程中沉积，这降低了锗除气。低温过程可以是ALD过程。

10. 发明授权

US07713834B2 Method of forming isolation regions for integrated circuits 有权
标题翻译：形成集成电路隔离区的方法
公开(公告)号：US07713834B2
公开(公告)日：2010-05-11
申请号：US12205361
申请日：2008-09-05
申请人： Haihong Wang , Minh-Van Ngo , Qi Xiang , Paul R. Besser , Eric N. Paton , Ming-Ren Lin
发明人： Haihong Wang , Minh-Van Ngo , Qi Xiang , Paul R. Besser , Eric N. Paton , Ming-Ren Lin
IPC分类号： H01L21/76
CPC分类号： H01L21/76224 , H01L21/823481 , H01L29/1054
摘要： A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed from a semiconductor or metal layer which is deposited in a low temperature process which reduces germanium outgassing. The low temperature process can be a ALD process.
摘要翻译：集成电路（IC）的制造方法利用浅沟槽隔离（STI）技术。浅沟槽隔离技术用于应变硅（SMOS）工艺。用于沟槽的衬垫由半导体或金属层形成，该半导体或金属层在低温过程中沉积，这降低了锗除气。低温过程可以是ALD过程。

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