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1. 发明申请

US20110057216A1 Low profile optoelectronic device package 审中-公开
标题翻译：薄型光电器件封装
公开(公告)号：US20110057216A1
公开(公告)日：2011-03-10
申请号：US12584779
申请日：2009-09-10
申请人： Ming-Kuen Chiu , Chin-Ta Fan , Chien-Cheng Wei , Paul Panaccione
发明人： Ming-Kuen Chiu , Chin-Ta Fan , Chien-Cheng Wei , Paul Panaccione
IPC分类号： H01L33/00 , H01L31/0232
CPC分类号： H01L31/0203 , H01L33/54 , H01L2224/16225 , H01L2224/48091 , H01L2224/48247 , H01L2924/00014
摘要： A low profile optoelectronic device package has a matalized transparent substrate, a chip and a dam ring. The matalized transparent substrate has a transparent board, a window area, and a metal pattern formed on a face of the transparent board and around the window area and having at least one outer contact pad and at least two contact pads. An active face of the chip is mounted to the at least two inner contact pads and aligned to the window area. A bottom face of the chip, that is opposite to the active face is further added a soldering layer. The dam ring is sealed a joint between the chip and the matalized transparent substrate so as to define an air cavity among the chip, the matalized transparent substrate and the dam ring. The matalized transparent substrate is used as a substrate and an optical cover of a conventional device package, so the optoelectronic device package provides low profile, small area outline, low fabricating cost and high lighting efficiency.
摘要翻译：薄型光电子器件封装具有成熟的透明衬底，芯片和坝环。成熟的透明基板具有透明板，窗口区域和形成在透明板的表面上并且在窗口区域周围的金属图案，并且具有至少一个外部接触垫和至少两个接触垫。芯片的主动面被安装到至少两个内部接触垫并与窗口区域对准。芯片的与有源面相反的底面进一步添加了焊接层。该密封环密封在芯片和金属化的透明基板之间的接头，以便在芯片，成熟的透明基板和坝环之间形成空气腔。成熟的透明基板用作传统器件封装的基板和光学盖，因此光电子器件封装提供低轮廓，小面积轮廓，低制造成本和高照明效率。

2. 发明申请

US20140110159A1 STRESS-REDUCED CIRCUIT BOARD AND METHOD FOR FORMING THE SAME 有权
标题翻译：应力减小电路板及其形成方法
公开(公告)号：US20140110159A1
公开(公告)日：2014-04-24
申请号：US13960897
申请日：2013-08-07
申请人： Chien-Cheng Wei , Wu-Hui Cheng
发明人： Chien-Cheng Wei , Wu-Hui Cheng
IPC分类号： H05K1/02 , H05K3/06 , H05K3/00
CPC分类号： H05K1/0271 , H05K1/0265 , H05K1/0306 , H05K3/06 , H05K3/108 , H05K3/146 , H05K3/16 , H05K3/388 , H05K2201/0338 , H05K2201/09845 , H05K2203/058 , H05K2203/1476 , H05K2203/1572
摘要： A stress-reduced circuit board includes an insulating substrate, and first and second electrically conductive layers which are stacked one upon the other, and which respectively have peripheral marginal regions that are configured in a stepped arrangement. The first electrically conductive layer is configured to have an area dimension larger than that of the second electrically conductive layer and a thickness not greater than that of the second electrically conductive layer so as to minimize stress caused by a difference in coefficients of thermal expansion between the insulating substrate and the first and second electrically conductive layers.
摘要翻译：应力降低电路板包括绝缘基板以及彼此堆叠的第一和第二导电层，并且分别具有以阶梯式布置的周边边缘区域。第一导电层被配置为具有比第二导电层的面积尺寸更大的面积尺寸，并且其厚度不大于第二导电层的厚度，以便使由于第二导电层之间的热膨胀系数的差异而引起的应力最小化绝缘基板和第一和第二导电层。

3. 发明申请

US20080157210A1 High-linearity and high-power CMOS structure and manufacturing method for the same 审中-公开
标题翻译：高线性度和高功率CMOS结构及制造方法相同
公开(公告)号：US20080157210A1
公开(公告)日：2008-07-03
申请号：US11645915
申请日：2006-12-27
申请人： Hsien-Chin Chiu , Chien-Cheng Wei , Wei-Hsien Lee , Wu-Shiung Feng
发明人： Hsien-Chin Chiu , Chien-Cheng Wei , Wei-Hsien Lee , Wu-Shiung Feng
IPC分类号： H01L29/94
CPC分类号： H01L29/402 , H01L29/456 , H01L29/4933 , H01L29/66575 , H01L29/78
摘要： This invention relates to a high-linearity and high-power CMOS structure and a method for the same and particularly to a field plate technology that is applied to a CMOS component, in which the field plate is formed on a dielectric layer of the CMOS, being arranged above a gate and a drain. An electric field is provided to significantly improve the RF linearity and output power of the CMOS component.
摘要翻译：本发明涉及一种高线性和高功率CMOS结构及其应用于CMOS元件的场板技术的方法，其中场板形成在CMOS的电介质层上，布置在闸门和排水沟上方。提供电场以显着地提高CMOS部件的RF线性度和输出功率。

4. 发明授权

US09468091B2 Stress-reduced circuit board and method for forming the same 有权
标题翻译：应力减小电路板及其形成方法
公开(公告)号：US09468091B2
公开(公告)日：2016-10-11
申请号：US13960897
申请日：2013-08-07
申请人： Chien-Cheng Wei , Wu-Hui Cheng
发明人： Chien-Cheng Wei , Wu-Hui Cheng
IPC分类号： H05K1/02 , H05K3/06 , H05K3/00 , H05K1/03 , H05K3/10 , H05K3/14 , H05K3/16 , H05K3/38
CPC分类号： H05K1/0271 , H05K1/0265 , H05K1/0306 , H05K3/06 , H05K3/108 , H05K3/146 , H05K3/16 , H05K3/388 , H05K2201/0338 , H05K2201/09845 , H05K2203/058 , H05K2203/1476 , H05K2203/1572
摘要： A stress-reduced circuit board includes an insulating substrate, and first and second electrically conductive layers which are stacked one upon the other, and which respectively have peripheral marginal regions that are configured in a stepped arrangement. The first electrically conductive layer is configured to have an area dimension larger than that of the second electrically conductive layer and a thickness not greater than that of the second electrically conductive layer so as to minimize stress caused by a difference in coefficients of thermal expansion between the insulating substrate and the first and second electrically conductive layers.
摘要翻译：应力降低电路板包括绝缘基板以及彼此堆叠的第一和第二导电层，并且分别具有以阶梯式布置的周边边缘区域。第一导电层被配置为具有比第二导电层的面积尺寸更大的面积尺寸，并且其厚度不大于第二导电层的厚度，以便使由于第二导电层之间的热膨胀系数的差异而引起的应力最小化绝缘基板和第一和第二导电层。

5. 发明申请

US20080318372A1 MANUFACTURING METHOD OF HIGH-LINEARITY AND HIGH-POWER CMOS STRUCTURE 审中-公开
标题翻译：高功率CMOS结构的制造方法
公开(公告)号：US20080318372A1
公开(公告)日：2008-12-25
申请号：US12199537
申请日：2008-08-27
申请人： Hsien-Chin Chiu , Chien-Cheng Wei , Wei-Hsien Lee , Wu-Shiung Feng
发明人： Hsien-Chin Chiu , Chien-Cheng Wei , Wei-Hsien Lee , Wu-Shiung Feng
IPC分类号： H01L21/8238
CPC分类号： H01L29/402 , H01L29/456 , H01L29/4933 , H01L29/66575 , H01L29/78
摘要： This invention relates to a method for making a high-linearity and high-power CMOS structure and particularly to a field plate technology that is applied to a CMOS component, in which the field plate is formed on a dielectric layer of the CMOS, being arranged above a gate and a drain. An electric field is provided to significantly improve the RF linearity and output power of the CMOS component.
摘要翻译：本发明涉及一种用于制造高线性和高功率CMOS结构的方法，特别涉及一种应用于CMOS元件的场板技术，其中场板形成在CMOS的电介质层上，布置在闸门和排水沟之上。提供电场以显着地提高CMOS部件的RF线性度和输出功率。

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