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1. 发明申请

US20100039304A1 DIGITAL TO ANALOG CONVERTER AND METHOD THEREOF 有权
标题翻译：数字到模拟转换器及其方法
公开(公告)号：US20100039304A1
公开(公告)日：2010-02-18
申请号：US12338633
申请日：2008-12-18
申请人： Jer-Hau Hsu , Tien-Yen Wang , Hsin-Yi Ho
发明人： Jer-Hau Hsu , Tien-Yen Wang , Hsin-Yi Ho
IPC分类号： H03M1/78
CPC分类号： H03M1/808
摘要： A digital to analog converter (DAC) has a plurality of transistor-resistor units connected in a string. Each of the transistor-resistor units of the DAC has a pair of transistors that are turned on/off by a pair of complementary control signals. Since the two transistors of each transistor-resistor unit are positioned symmetrically, an equivalent resistance would be determined precisely according to received digital codes, such that an output voltage of the DAC could be adjusted precisely based on the equivalent resistance.
摘要翻译：数模转换器（DAC）具有串联连接的多个晶体管电阻单元。 DAC的每个晶体管 - 电阻单元都有一对晶体管，通过一对互补控制信号导通/截止。由于每个晶体管 - 电阻器单元的两个晶体管对称地定位，所以根据接收到的数字代码精确地确定等效电阻，使得可以基于等效电阻精确地调整DAC的输出电压。

2. 发明授权

US07812754B2 Digital to analog converter and method thereof 有权
标题翻译：数模转换器及其方法
公开(公告)号：US07812754B2
公开(公告)日：2010-10-12
申请号：US12338633
申请日：2008-12-18
申请人： Jer-Hau Hsu , Tien-Yen Wang , Hsin-Yi Ho
发明人： Jer-Hau Hsu , Tien-Yen Wang , Hsin-Yi Ho
IPC分类号： H03M1/78
CPC分类号： H03M1/808
摘要： A digital to analog converter (DAC) has a plurality of transistor-resistor units connected in a string. Each of the transistor-resistor units of the DAC has a pair of transistors that are turned on/off by a pair of complementary control signals. Since the two transistors of each transistor-resistor unit are positioned symmetrically, an equivalent resistance would be determined precisely according to received digital codes, such that an output voltage of the DAC could be adjusted precisely based on the equivalent resistance.
摘要翻译：数模转换器（DAC）具有串联连接的多个晶体管电阻单元。 DAC的每个晶体管 - 电阻单元都有一对晶体管，通过一对互补控制信号导通/截止。由于每个晶体管 - 电阻器单元的两个晶体管对称地定位，所以根据接收到的数字代码精确地确定等效电阻，使得可以基于等效电阻精确地调整DAC的输出电压。

3. 发明授权

US07697350B2 Low couple effect bit-line voltage generator 有权
标题翻译：低耦合效应位线电压发生器
公开(公告)号：US07697350B2
公开(公告)日：2010-04-13
申请号：US11967677
申请日：2007-12-31
申请人： Jer-Hau Hsu , Yung Feng Lin
发明人： Jer-Hau Hsu , Yung Feng Lin
IPC分类号： G11C5/14
CPC分类号： G11C7/12
摘要： A bit-line voltage generator is provided. The bit-line voltage generator includes a discharge enhanced bias source and a switch unit. The switch unit includes a clamp transistor having a source, a gate connected to the discharge enhanced bias source, and a drain receiving a voltage; a switch transistor having a gate receiving a control signal, a drain connected to the source of the clamp transistor, and a source connected to a memory array, wherein a parasitic capacitor exists between the gate and the source of the clamp transistor; a resistor having a first terminal connected to the drain of the switch transistor, and a second terminal connected to ground; and a capacitor having a first terminal connected to the drain of the switch transistor, and a second terminal connected to ground, wherein a charge in the parasitic capacitor, when the switch transistor is turned on, is almost identical to that when the switch transistor is turned off, so that a couple effect between the switch unit and the discharge enhanced bias source is reduced, thereby stabilizing a bias applied to the memory array.
摘要翻译：提供了位线电压发生器。位线电压发生器包括放电增强偏置源和开关单元。开关单元包括具有源极，连接到放电增强偏置源的栅极和接收电压的漏极的钳位晶体管; 具有接收控制信号的栅极的开关晶体管，连接到钳位晶体管的源极的漏极和连接到存储器阵列的源极，其中寄生电容器存在于钳位晶体管的栅极和源极之间; 电阻器，其具有连接到开关晶体管的漏极的第一端子和连接到地的第二端子; 以及电容器，其具有连接到开关晶体管的漏极的第一端子和连接到地的第二端子，其中当开关晶体管导通时，寄生电容器中的电荷几乎与开关晶体管为关闭，使得开关单元和放电增强偏置源之间的耦合效应降低，从而稳定施加到存储器阵列的偏置。

4. 发明授权

US07586802B2 Memory, bit-line pre-charge circuit and bit-line pre-charge method 有权
标题翻译：存储器，位线预充电电路和位线预充电方法
公开(公告)号：US07586802B2
公开(公告)日：2009-09-08
申请号：US12027333
申请日：2008-02-07
申请人： Jer-Hau Hsu , Fu-Nian Liang , Yufe-Feng Lin
发明人： Jer-Hau Hsu , Fu-Nian Liang , Yufe-Feng Lin
IPC分类号： G11C7/00
CPC分类号： G11C7/12
摘要： A memory is provided. The memory includes a memory cell, a clamp transistor, an inverter, a bit line, a pre-charge path and a detector and controller circuit. The memory is coupled to the clamp transistor. The clamp transistor has a first end, a second end and a control end. The inverter has an input end electrically connected to the second end of the clamp transistor and an output end electrically connected to the control end of the clamp transistor. The bit line is electrically connected to the second end of the clamp transistor and the input end of the inverter and has a bit-line voltage thereon. The pre-charge path is electrically connected to the first end of the clamp transistor through a node having a sensing voltage thereon. The detector and controller circuit is electrically connected to the first end of the clamp transistor and the pre-charge path for detecting the sensing voltage in order to open the pre-charge path to raise the bit-line voltage when the sensing voltage is at a low level and close the pre-charge path when the sensing voltage is at a high level.
摘要翻译：提供记忆。存储器包括存储单元，钳位晶体管，反相器，位线，预充电路径以及检测器和控制器电路。存储器耦合到钳位晶体管。钳位晶体管具有第一端，第二端和控制端。逆变器具有电连接到钳位晶体管的第二端的输入端和电连接到钳位晶体管的控制端的输出端。位线电连接到钳位晶体管的第二端和反相器的输入端，并在其上具有位线电压。预充电路径通过其上具有感测电压的节点电连接到钳位晶体管的第一端。检测器和控制器电路电连接到钳位晶体管的第一端和用于检测感测电压的预充电路径，以便当感测电压为一个时，打开预充电路径以升高位线电压低电平并且当感测电压处于高电平时闭合预充电路径。

5. 发明申请

US20100157694A1 LOW COUPLE EFFECT BIT-LINE VOLTAGE GENERATOR 有权
标题翻译：低耦合效应点对线电压发生器
公开(公告)号：US20100157694A1
公开(公告)日：2010-06-24
申请号：US12715504
申请日：2010-03-02
申请人： Jer-Hau Hsu , Yung Feng Lin
发明人： Jer-Hau Hsu , Yung Feng Lin
IPC分类号： G11C5/14 , H03K17/687
CPC分类号： G11C7/12
摘要： A bit-line voltage generator is provided. The bit-line voltage generator includes a discharge enhanced bias source and a switch unit. The switch unit includes a clamp transistor having a source, a gate connected to the discharge enhanced bias source, and a drain receiving a voltage; a switch transistor having a gate receiving a control signal, a drain connected to the source of the clamp transistor, and a source connected to a memory array, wherein a parasitic capacitor exists between the gate and the source of the clamp transistor; a resistor having a first terminal connected to the drain of the switch transistor, and a second terminal connected to ground; and a capacitor having a first terminal connected to the drain of the switch transistor, and a second terminal connected to ground, wherein a charge in the parasitic capacitor, when the switch transistor is turned on, is almost identical to that when the switch transistor is turned off, so that a couple effect between the switch unit and the discharge enhanced bias source is reduced, thereby stabilizing a bias applied to the memory array.
摘要翻译：提供了位线电压发生器。位线电压发生器包括放电增强偏置源和开关单元。开关单元包括具有源极，连接到放电增强偏置源的栅极和接收电压的漏极的钳位晶体管; 具有接收控制信号的栅极的开关晶体管，连接到钳位晶体管的源极的漏极和连接到存储器阵列的源极，其中寄生电容器存在于钳位晶体管的栅极和源极之间; 电阻器，其具有连接到开关晶体管的漏极的第一端子和连接到地的第二端子; 以及电容器，其具有连接到开关晶体管的漏极的第一端子和连接到地的第二端子，其中当开关晶体管导通时，寄生电容器中的电荷几乎与开关晶体管为关闭，使得开关单元和放电增强偏置源之间的耦合效应降低，从而稳定施加到存储器阵列的偏置。

6. 发明授权

US08077528B2 Low couple effect bit-line voltage generator 有权
标题翻译：低耦合效应位线电压发生器
公开(公告)号：US08077528B2
公开(公告)日：2011-12-13
申请号：US12715504
申请日：2010-03-02
申请人： Jer-Hau Hsu , Yung Feng Lin
发明人： Jer-Hau Hsu , Yung Feng Lin
IPC分类号： G11C5/14
CPC分类号： G11C7/12
摘要： A bit-line voltage generator is provided. The bit-line voltage generator includes a discharge enhanced bias source and a switch unit. The switch unit includes a clamp transistor having a source, a gate connected to the discharge enhanced bias source, and a drain receiving a voltage; a switch transistor having a gate receiving a control signal, a drain connected to the source of the clamp transistor, and a source connected to a memory array, wherein a parasitic capacitor exists between the gate and the source of the clamp transistor; a resistor having a first terminal connected to the drain of the switch transistor, and a second terminal connected to ground; and a capacitor having a first terminal connected to the drain of the switch transistor, and a second terminal connected to ground, wherein a charge in the parasitic capacitor, when the switch transistor is turned on, is almost identical to that when the switch transistor is turned off, so that a couple effect between the switch unit and the discharge enhanced bias source is reduced, thereby stabilizing a bias applied to the memory array.
摘要翻译：提供了位线电压发生器。位线电压发生器包括放电增强偏置源和开关单元。开关单元包括具有源极，连接到放电增强偏置源的栅极和接收电压的漏极的钳位晶体管; 具有接收控制信号的栅极的开关晶体管，连接到钳位晶体管的源极的漏极和连接到存储器阵列的源极，其中寄生电容器存在于钳位晶体管的栅极和源极之间; 电阻器，其具有连接到开关晶体管的漏极的第一端子和连接到地的第二端子; 以及电容器，其具有连接到开关晶体管的漏极的第一端子和连接到地的第二端子，其中当开关晶体管导通时，寄生电容器中的电荷几乎与开关晶体管为关闭，使得开关单元和放电增强偏置源之间的耦合效应降低，从而稳定施加到存储器阵列的偏置。

7. 发明申请

US20090201747A1 MEMORY, BIT-LINE PRE-CHARGE CIRCUIT AND BIT-LINE PRE-CHARGE METHOD 有权
标题翻译：存储器，位线预充电电路和位线预充电方法
公开(公告)号：US20090201747A1
公开(公告)日：2009-08-13
申请号：US12027333
申请日：2008-02-07
申请人： Jer-Hau Hsu , Fu-Nian Liang , Yufe-Feng Lin
发明人： Jer-Hau Hsu , Fu-Nian Liang , Yufe-Feng Lin
IPC分类号： G11C7/00
CPC分类号： G11C7/12
摘要： A memory is provided. The memory includes a memory cell, a clamp transistor, an inverter, a bit line, a pre-charge path and a detector and controller circuit. The memory is coupled to the clamp transistor. The clamp transistor has a first end, a second end and a control end. The inverter has an input end electrically connected to the second end of the clamp transistor and an output end electrically connected to the control end of the clamp transistor. The bit line is electrically connected to the second end of the clamp transistor and the input end of the inverter and has a bit-line voltage thereon. The pre-charge path is electrically connected to the first end of the clamp transistor through a node having a sensing voltage thereon. The detector and controller circuit is electrically connected to the first end of the clamp transistor and the pre-charge path for detecting the sensing voltage in order to open the pre-charge path to raise the bit-line voltage when the sensing voltage is at a low level and close the pre-charge path when the sensing voltage is at a high level.
摘要翻译：提供记忆。存储器包括存储单元，钳位晶体管，反相器，位线，预充电路径以及检测器和控制器电路。存储器耦合到钳位晶体管。钳位晶体管具有第一端，第二端和控制端。逆变器具有电连接到钳位晶体管的第二端的输入端和电连接到钳位晶体管的控制端的输出端。位线电连接到钳位晶体管的第二端和反相器的输入端，并在其上具有位线电压。预充电路径通过其上具有感测电压的节点电连接到钳位晶体管的第一端。检测器和控制器电路电连接到钳位晶体管的第一端和用于检测感测电压的预充电路径，以便当感测电压为一个时，打开预充电路径以升高位线电压低电平并且当感测电压处于高电平时闭合预充电路径。

8. 发明申请

US20090168554A1 LOW COUPLE EFFECT BIT-LINE VOLTAGE GENERATOR 有权
标题翻译：低耦合效应点对线电压发生器
公开(公告)号：US20090168554A1
公开(公告)日：2009-07-02
申请号：US11967677
申请日：2007-12-31
申请人： Jer-Hau Hsu , Yung Feng Lin
发明人： Jer-Hau Hsu , Yung Feng Lin
IPC分类号： G11C7/12
CPC分类号： G11C7/12
摘要： A bit-line voltage generator is provided. The bit-line voltage generator includes a discharge enhanced bias source and a switch unit. The switch unit includes a clamp transistor having a source, a gate connected to the discharge enhanced bias source, and a drain receiving a voltage; a switch transistor having a gate receiving a control signal, a drain connected to the source of the clamp transistor, and a source connected to a memory array, wherein a parasitic capacitor exists between the gate and the source of the clamp transistor; a resistor having a first terminal connected to the drain of the switch transistor, and a second terminal connected to ground; and a capacitor having a first terminal connected to the drain of the switch transistor, and a second terminal connected to ground, wherein a charge in the parasitic capacitor, when the switch transistor is turned on, is almost identical to that when the switch transistor is turned off, so that a couple effect between the switch unit and the discharge enhanced bias source is reduced, thereby stabilizing a bias applied to the memory array.
摘要翻译：提供了位线电压发生器。位线电压发生器包括放电增强偏置源和开关单元。开关单元包括具有源极，连接到放电增强偏置源的栅极和接收电压的漏极的钳位晶体管; 具有接收控制信号的栅极的开关晶体管，连接到钳位晶体管的源极的漏极和连接到存储器阵列的源极，其中寄生电容器存在于钳位晶体管的栅极和源极之间; 电阻器，其具有连接到开关晶体管的漏极的第一端子和连接到地的第二端子; 以及电容器，其具有连接到开关晶体管的漏极的第一端子和连接到地的第二端子，其中当开关晶体管导通时，寄生电容器中的电荷几乎与开关晶体管为关闭，使得开关单元和放电增强偏置源之间的耦合效应降低，由此稳定施加到存储器阵列的偏置。

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