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1. 发明授权

US07817386B2 ESD protection circuit for IC with separated power domains 有权
标题翻译：具有分离电源域的IC的ESD保护电路
公开(公告)号：US07817386B2
公开(公告)日：2010-10-19
申请号：US11907206
申请日：2007-10-10
申请人： Ming-Dou Ker , Yuan-Wen Hsiao , Ryan Hsin-Chin Jiang
发明人： Ming-Dou Ker , Yuan-Wen Hsiao , Ryan Hsin-Chin Jiang
IPC分类号： H02H9/00
CPC分类号： H01L27/0266 , H01L2924/0002 , H01L2924/00
摘要： An ESD protection circuit suitable for applying in an integrated circuit with separated power domains is provided. The circuit includes a P-type MOSFET coupled between a first circuit in a first power domain and a second circuit in a second power domain. A source terminal of the P-type MOSFET is coupled to a connection node for connecting the first circuit and the second circuit. A gate terminal of the P-type MOSFET is coupled to a positive power line of the second power domain. A drain terminal of the P-type MOSFET is coupled to a negative power line of the second power domain. A body terminal of the P-type MOSFET is also coupled to the connection node.
摘要翻译：提供一种适用于具有分离电源域的集成电路中的ESD保护电路。电路包括耦合在第一电源域中的第一电路和第二电源域中的第二电路之间的P型MOSFET。 P型MOSFET的源极端子连接到用于连接第一电路和第二电路的连接节点。 P型MOSFET的栅极端子耦合到第二电源域的正电源线。 P型MOSFET的漏极端子耦合到第二电源域的负电源线。 P型MOSFET的体式端子也耦合到连接节点。

2. 发明授权

US07974053B2 ESD protection circuit for differential I/O pair 有权
标题翻译：差分I / O对的ESD保护电路
公开(公告)号：US07974053B2
公开(公告)日：2011-07-05
申请号：US12129230
申请日：2008-05-29
申请人： Ming-Dou Ker , Yuan-Wen Hsiao , Hsin-Chin Jiang
发明人： Ming-Dou Ker , Yuan-Wen Hsiao , Hsin-Chin Jiang
IPC分类号： H02H9/00 , H02H3/20 , H02H9/04
CPC分类号： H01L27/0251 , H03F1/523 , H03F3/45183
摘要： An ESD protection circuit for a differential I/O pair is provided. The circuit includes an ESD detection circuit, a discharge device, and four diodes. The first diode is coupled between the first I/O pin and the discharge device in a forward direction toward the discharge device. The second diode is coupled between the second I/O pin and the discharge device in a forward direction toward the second I/O pin. The third diode is coupled between the discharge device and the positive power line in a forward direction toward the positive power line. The fourth diode is coupled between the discharge device and the negative power line in a forward direction toward the discharge device. Via an output end, the ESD detection circuit triggers the discharge device during ESD events.
摘要翻译：提供了用于差分I / O对的ESD保护电路。该电路包括ESD检测电路，放电装置和四个二极管。第一二极管在朝向放电装置的正向方向上在第一I / O引脚和放电装置之间耦合。第二二极管在第二I / O引脚和放电装置之间朝向第二I / O引脚向前方连接。第三二极管朝着正电力线向前方连接在放电装置和正电力线之间。第四二极管在放电装置和负电源线之间朝向放电装置向前方连接。通过输出端，ESD检测电路在ESD事件期间触发放电装置。

3. 发明申请

US20090021872A1 ESD protection circuit with active triggering 有权
标题翻译：具有主动触发的ESD保护电路
公开(公告)号：US20090021872A1
公开(公告)日：2009-01-22
申请号：US11826634
申请日：2007-07-17
申请人： Ming-Dou Ker , Yuan-Wen Hsiao , Ryan Hsin-Chin Jiang
发明人： Ming-Dou Ker , Yuan-Wen Hsiao , Ryan Hsin-Chin Jiang
IPC分类号： H02H3/22
CPC分类号： H01L27/0266 , H01L2924/0002 , H01L2924/00
摘要： An ESD protection circuit is provided. The circuit includes a discharging component, a diode, and an ESD detection circuit. The discharging component is coupled between an input/output pad and a first power line of an IC. The diode is coupled between the input/output pad and a second power line of the IC in a forward direction toward the second power line. The ESD detection circuit includes a capacitor, a resistor, and a triggering component. The capacitor and the resistor are formed in series and coupled between the first power line and the second power line. The triggering component has a positive power end coupled to the input/output pad and a negative power end coupled to the first power line. An input of the triggering component is coupled to a node between the capacitor and the resistor.
摘要翻译：提供ESD保护电路。电路包括放电元件，二极管和ESD检测电路。放电元件耦合在IC的输入/输出焊盘和第一电源线之间。所述二极管在所述输入/输出焊盘和所述IC的第二电源线之间朝向所述第二电力线向前方连接。 ESD检测电路包括电容器，电阻器和触发部件。电容器和电阻器串联形成并耦合在第一电源线和第二电源线之间。触发组件具有耦合到输入/输出焊盘的正功率端和耦合到第一电源线的负功率端。触发元件的输入耦合到电容器和电阻器之间的节点。

4. 发明授权

US07889470B2 ESD protection circuit with active triggering 有权
标题翻译：具有主动触发的ESD保护电路
公开(公告)号：US07889470B2
公开(公告)日：2011-02-15
申请号：US12656495
申请日：2010-02-01
申请人： Ming-Dou Ker , Yuan-Wen Hsiao , Ryan Hsin-Chin Jiang
发明人： Ming-Dou Ker , Yuan-Wen Hsiao , Ryan Hsin-Chin Jiang
IPC分类号： H02H9/00
CPC分类号： H01L27/0266 , H01L2924/0002 , H01L2924/00
摘要： An ESD protection circuit is provided. The circuit includes a discharging component, a diode, and an ESD detection circuit. The discharging component is coupled between an input/output pad and a first power line of an IC. The diode is coupled between the input/output pad and a second power line of the IC in a forward direction toward the second power line. The ESD detection circuit includes a capacitor, a resistor, and a triggering component. The capacitor and the resistor are formed in series and coupled between the first power line and the second power line. The triggering component has a positive power end coupled to the input/output pad and a negative power end coupled to the first power line. An input of the triggering component is coupled to a node between the capacitor and the resistor.
摘要翻译：提供ESD保护电路。电路包括放电元件，二极管和ESD检测电路。放电元件耦合在IC的输入/输出焊盘和第一电源线之间。所述二极管在所述输入/输出焊盘和所述IC的第二电源线之间朝向所述第二电力线向前方连接。 ESD检测电路包括电容器，电阻器和触发部件。电容器和电阻器串联形成并耦合在第一电源线和第二电源线之间。触发组件具有耦合到输入/输出焊盘的正功率端和耦合到第一电源线的负功率端。触发元件的输入耦合到电容器和电阻器之间的节点。

5. 发明申请

US20100142107A1 ESD protection circuit with active triggering 有权
公开(公告)号：US20100142107A1
公开(公告)日：2010-06-10
申请号：US12656495
申请日：2010-02-01
申请人： Ming-Dou Ker , Yuan-Wen Hsiao , Ryan Hsin-Chin Jiang
发明人： Ming-Dou Ker , Yuan-Wen Hsiao , Ryan Hsin-Chin Jiang
IPC分类号： H02H9/04
CPC分类号： H01L27/0266 , H01L2924/0002 , H01L2924/00
摘要： An ESD protection circuit is provided. The circuit includes a discharging component, a diode, and an ESD detection circuit. The discharging component is coupled between an input/output pad and a first power line of an IC. The diode is coupled between the input/output pad and a second power line of the IC in a forward direction toward the second power line. The ESD detection circuit includes a capacitor, a resistor, and a triggering component. The capacitor and the resistor are formed in series and coupled between the first power line and the second power line. The triggering component has a positive power end coupled to the input/output pad and a negative power end coupled to the first power line. An input of the triggering component is coupled to a node between the capacitor and the resistor.

6. 发明授权

US07656627B2 ESD protection circuit with active triggering 有权
标题翻译：具有主动触发的ESD保护电路
公开(公告)号：US07656627B2
公开(公告)日：2010-02-02
申请号：US11826634
申请日：2007-07-17
申请人： Ming-Dou Ker , Yuan-Wen Hsiao , Ryan Hsin-Chin Jiang
发明人： Ming-Dou Ker , Yuan-Wen Hsiao , Ryan Hsin-Chin Jiang
IPC分类号： H02H9/00
CPC分类号： H01L27/0266 , H01L2924/0002 , H01L2924/00
摘要： An ESD protection circuit is provided. The circuit includes a discharging component, a diode, and an ESD detection circuit. The discharging component is coupled between an input/output pad and a first power line of an IC. The diode is coupled between the input/output pad and a second power line of the IC in a forward direction toward the second power line. The ESD detection circuit includes a capacitor, a resistor, and a triggering component. The capacitor and the resistor are formed in series and coupled between the first power line and the second power line. The triggering component has a positive power end coupled to the input/output pad and a negative power end coupled to the first power line. An input of the triggering component is coupled to a node between the capacitor and the resistor.
摘要翻译：提供ESD保护电路。电路包括放电元件，二极管和ESD检测电路。放电元件耦合在IC的输入/输出焊盘和第一电源线之间。所述二极管在所述输入/输出焊盘和所述IC的第二电源线之间朝向所述第二电力线向前方连接。 ESD检测电路包括电容器，电阻器和触发部件。电容器和电阻器串联形成并耦合在第一电源线和第二电源线之间。触发组件具有耦合到输入/输出焊盘的正功率端和耦合到第一电源线的负功率端。触发元件的输入耦合到电容器和电阻器之间的节点。

7. 发明授权

US07675724B2 Electrostatic discharge protection device for mixed voltage interface 有权
标题翻译：用于混合电压接口的静电放电保护装置
公开(公告)号：US07675724B2
公开(公告)日：2010-03-09
申请号：US12114485
申请日：2008-05-02
申请人： Ming-Dou Ker , Kuo-Chun Hsu , Hsin-Chin Jiang
发明人： Ming-Dou Ker , Kuo-Chun Hsu , Hsin-Chin Jiang
IPC分类号： H02H3/22
CPC分类号： H01L27/0266
摘要： An electrostatic discharge protection circuit that includes at least two transistors connected in a stacked configuration, a first diffusion region of a first dopant type shared by two adjacent transistors, and a second diffusion region of a second dopant type formed in the first diffusion region. A substrate-triggered site is induced into the device structure of the stacked transistors to improve ESD robustness and turn-on speed. An area-efficient layout to realize the stacked transistors is proposed. The stacked transistors may be implemented in ESD protection circuits with a mixed-voltage I/O interface, or in integrated circuits with multiple power supplies. The stacked transistors are fabricated without using a thick-gate mask.
摘要翻译：一种静电放电保护电路，其包括以堆叠结构连接的至少两个晶体管，由两个相邻晶体管共享的第一掺杂剂类型的第一扩散区域和形成在第一扩散区域中的第二掺杂剂类型的第二扩散区域。衬底触发位置被引入堆叠晶体管的器件结构，以提高ESD稳健性和开启速度。提出了实现堆叠晶体管的区域效率布局。堆叠晶体管可以在具有混合电压I / O接口的ESD保护电路中或在具有多个电源的集成电路中实现。在不使用厚栅掩模的情况下制造堆叠晶体管。

8. 发明申请

US20090135533A1 Power-rail ESD protection circuit with ultra low gate leakage 有权
标题翻译：电源轨道ESD保护电路具有超低门极泄漏
公开(公告)号：US20090135533A1
公开(公告)日：2009-05-28
申请号：US11987222
申请日：2007-11-28
申请人： Ming-Dou Ker , Chin-Hao Chen , Ryan Hsin-Chin Jiang
发明人： Ming-Dou Ker , Chin-Hao Chen , Ryan Hsin-Chin Jiang
IPC分类号： H02H9/04
CPC分类号： H02H9/046
摘要： An ESD protection circuit including a clamping module and a detecting module is provided. The clamping module is coupled between a positive power line and a negative power line. The detecting module includes a triggering unit, a resistor, and a MOS capacitor. An output terminal of the triggering unit is used for triggering the clamping module. The resistor is coupled between the positive power line and an input terminal of the triggering unit. The MOS capacitor has a first end and a second end. The first end is coupled to the input terminal of the triggering unit. During a normal power operation, a switching terminal of the triggering unit enables the second end of the MOS capacitor to be coupled with the positive power line. Thereby, the gate tunneling leakage is eliminated and the problem of mistriggering is prevented.
摘要翻译：提供了包括夹紧模块和检测模块的ESD保护电路。夹紧模块耦合在正电源线和负电源线之间。检测模块包括触发单元，电阻器和MOS电容器。触发单元的输出端子用于触发夹紧模块。电阻器耦合在正电源线和触发单元的输入端之间。 MOS电容器具有第一端和第二端。第一端耦合到触发单元的输入端。在正常电力操作期间，触发单元的开关端子使MOS电容器的第二端与正电源线耦合。由此，消除了栅极隧道泄漏，并且防止了错误捕捉的问题。

9. 发明申请

US20090009229A1 HIGH/LOW VOLTAGE TOLERANT INTERFACE CIRCUIT AND CRYSTAL OSCILLATOR CIRCUIT 有权
标题翻译：高/低电压耐受接口电路和晶体振荡器电路
公开(公告)号：US20090009229A1
公开(公告)日：2009-01-08
申请号：US11773966
申请日：2007-07-06
申请人： Ming-Dou Ker , Hung-Tai Liao , Ryan Hsin-Chin Jiang
发明人： Ming-Dou Ker , Hung-Tai Liao , Ryan Hsin-Chin Jiang
IPC分类号： H03L5/00
CPC分类号： H03B5/36
摘要： A high/low voltage tolerant interface circuit and a crystal oscillator circuit using the same are provided herein. The interface circuit includes a first transistor, a bulk-voltage generator module and an bias module. The first transistor includes a gate, a first source/drain, a bulk coupled to the first source/drain of the first transistor and a second source/drain coupled to an input node. The bulk-voltage generator module is, used to determine whether a first voltage or a predetermined voltage is being provided to the bulk of the first transistor according to the voltage of the input node. The bias module is coupled to the gate of the first transistor. The bias module is used to provide an bias voltage to the gate of the first transistor and makes the first transistor conduct in order to control the voltage of the second source/drain voltage of the first transistor.
摘要翻译：本文提供了高/低电压容限接口电路和使用其的晶体振荡器电路。接口电路包括第一晶体管，体电压发生器模块和偏置模块。第一晶体管包括栅极，第一源极/漏极，耦合到第一晶体管的第一源极/漏极的体，以及耦合到输入节点的第二源极/漏极。大容量电压发生器模块用于根据输入节点的电压确定是否向第一晶体管本体提供第一电压或预定电压。偏置模块耦合到第一晶体管的栅极。偏置模块用于向第一晶体管的栅极提供偏置电压，并使第一晶体管导通，以便控制第一晶体管的第二源极/漏极电压的电压。

10. 发明申请

US20070188952A1 ON-CHIP LATCH-UP PROTECTION CIRCUIT 有权
标题翻译：片上保护电路
公开(公告)号：US20070188952A1
公开(公告)日：2007-08-16
申请号：US11618674
申请日：2006-12-29
申请人： Ming-Dou Ker , Jang-Jie Peng , Hsin-Chin Jiang
发明人： Ming-Dou Ker , Jang-Jie Peng , Hsin-Chin Jiang
IPC分类号： G01S13/08 , H02H9/00
CPC分类号： H01L27/0248 , H03K17/0822
摘要： An on-chip latch-up protection circuit. The lath-up protection circuit includes a core circuit, a power switch, and a current extractor. The power switch controls major current flowing through the core circuit. The current extractor detects amplitude of the major current. The power switch, the core circuit and the current extractor are coupled in series between a relatively-high power line and a relatively-low power line. When the major current surpasses a predetermined amplitude, the power switch is turned off, causing latch-up stops.
摘要翻译：一个片内闭锁保护电路。上拉保护电路包括核心电路，电源开关和电流提取器。电源开关控制流经核心电路的大电流。当前提取器检测主电流的幅度。电源开关，核心电路和电流提取器串联在相对较高的电力线和相对低的电力线之间。当主电流超过预定幅度时，电源开关被关闭，导致闭锁停止。

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