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1. 发明申请

US20090009229A1 HIGH/LOW VOLTAGE TOLERANT INTERFACE CIRCUIT AND CRYSTAL OSCILLATOR CIRCUIT 有权
标题翻译：高/低电压耐受接口电路和晶体振荡器电路
公开(公告)号：US20090009229A1
公开(公告)日：2009-01-08
申请号：US11773966
申请日：2007-07-06
申请人： Ming-Dou Ker , Hung-Tai Liao , Ryan Hsin-Chin Jiang
发明人： Ming-Dou Ker , Hung-Tai Liao , Ryan Hsin-Chin Jiang
IPC分类号： H03L5/00
CPC分类号： H03B5/36
摘要： A high/low voltage tolerant interface circuit and a crystal oscillator circuit using the same are provided herein. The interface circuit includes a first transistor, a bulk-voltage generator module and an bias module. The first transistor includes a gate, a first source/drain, a bulk coupled to the first source/drain of the first transistor and a second source/drain coupled to an input node. The bulk-voltage generator module is, used to determine whether a first voltage or a predetermined voltage is being provided to the bulk of the first transistor according to the voltage of the input node. The bias module is coupled to the gate of the first transistor. The bias module is used to provide an bias voltage to the gate of the first transistor and makes the first transistor conduct in order to control the voltage of the second source/drain voltage of the first transistor.
摘要翻译：本文提供了高/低电压容限接口电路和使用其的晶体振荡器电路。接口电路包括第一晶体管，体电压发生器模块和偏置模块。第一晶体管包括栅极，第一源极/漏极，耦合到第一晶体管的第一源极/漏极的体，以及耦合到输入节点的第二源极/漏极。大容量电压发生器模块用于根据输入节点的电压确定是否向第一晶体管本体提供第一电压或预定电压。偏置模块耦合到第一晶体管的栅极。偏置模块用于向第一晶体管的栅极提供偏置电压，并使第一晶体管导通，以便控制第一晶体管的第二源极/漏极电压的电压。

2. 发明授权

US07564317B2 High/low voltage tolerant interface circuit and crystal oscillator circuit 有权
标题翻译：高/低电压接口电路和晶体振荡电路
公开(公告)号：US07564317B2
公开(公告)日：2009-07-21
申请号：US11773966
申请日：2007-07-06
申请人： Ming-Dou Ker , Hung-Tai Liao , Ryan Hsin-Chin Jiang
发明人： Ming-Dou Ker , Hung-Tai Liao , Ryan Hsin-Chin Jiang
IPC分类号： H03B5/36
CPC分类号： H03B5/36
摘要： A high/low voltage tolerant interface circuit and a crystal oscillator circuit using the same are provided herein. The interface circuit includes a first transistor, a bulk-voltage generator module and an bias module. The first transistor includes a gate, a first source/drain, a bulk coupled to the first source/drain of the first transistor and a second source/drain coupled to an input node. The bulk-voltage generator module is, used to determine whether a first voltage or a predetermined voltage is being provided to the bulk of the first transistor according to the voltage of the input node. The bias module is coupled to the gate of the first transistor. The bias module is used to provide an bias voltage to the gate of the first transistor and makes the first transistor conduct in order to control the voltage of the second source/drain voltage of the first transistor.
摘要翻译：本文提供了高/低电压容限接口电路和使用其的晶体振荡器电路。接口电路包括第一晶体管，体电压发生器模块和偏置模块。第一晶体管包括栅极，第一源极/漏极，耦合到第一晶体管的第一源极/漏极的体，以及耦合到输入节点的第二源极/漏极。大容量电压发生器模块用于根据输入节点的电压确定是否向第一晶体管本体提供第一电压或预定电压。偏置模块耦合到第一晶体管的栅极。偏置模块用于向第一晶体管的栅极提供偏置电压，并使第一晶体管导通，以便控制第一晶体管的第二源极/漏极电压的电压。

3. 发明申请

US20090135533A1 Power-rail ESD protection circuit with ultra low gate leakage 有权
标题翻译：电源轨道ESD保护电路具有超低门极泄漏
公开(公告)号：US20090135533A1
公开(公告)日：2009-05-28
申请号：US11987222
申请日：2007-11-28
申请人： Ming-Dou Ker , Chin-Hao Chen , Ryan Hsin-Chin Jiang
发明人： Ming-Dou Ker , Chin-Hao Chen , Ryan Hsin-Chin Jiang
IPC分类号： H02H9/04
CPC分类号： H02H9/046
摘要： An ESD protection circuit including a clamping module and a detecting module is provided. The clamping module is coupled between a positive power line and a negative power line. The detecting module includes a triggering unit, a resistor, and a MOS capacitor. An output terminal of the triggering unit is used for triggering the clamping module. The resistor is coupled between the positive power line and an input terminal of the triggering unit. The MOS capacitor has a first end and a second end. The first end is coupled to the input terminal of the triggering unit. During a normal power operation, a switching terminal of the triggering unit enables the second end of the MOS capacitor to be coupled with the positive power line. Thereby, the gate tunneling leakage is eliminated and the problem of mistriggering is prevented.
摘要翻译：提供了包括夹紧模块和检测模块的ESD保护电路。夹紧模块耦合在正电源线和负电源线之间。检测模块包括触发单元，电阻器和MOS电容器。触发单元的输出端子用于触发夹紧模块。电阻器耦合在正电源线和触发单元的输入端之间。 MOS电容器具有第一端和第二端。第一端耦合到触发单元的输入端。在正常电力操作期间，触发单元的开关端子使MOS电容器的第二端与正电源线耦合。由此，消除了栅极隧道泄漏，并且防止了错误捕捉的问题。

4. 发明授权

US07817390B2 Power-rail ESD protection circuit with ultra low gate leakage 有权
标题翻译：电源轨道ESD保护电路具有超低门极泄漏
公开(公告)号：US07817390B2
公开(公告)日：2010-10-19
申请号：US12461237
申请日：2009-08-05
申请人： Ming-Dou Ker , Chin-Hao Chen , Ryan Hsin-Chin Jiang
发明人： Ming-Dou Ker , Chin-Hao Chen , Ryan Hsin-Chin Jiang
IPC分类号： H02H9/04
CPC分类号： H02H9/046
摘要： An ESD protection circuit including a clamping module and a detecting module is provided. The clamping module is coupled between a positive power line and a negative power line. The detecting module includes a triggering unit, a resistor, and a MOS capacitor. An output terminal of the triggering unit is used for triggering the clamping module. The resistor is coupled between the negative power line and an input terminal of the triggering unit. The MOS capacitor is coupled between the positive power line and an input terminal of the triggering unit for ESD protection. During a normal power operation, a switching terminal of the triggering unit enables the MOS capacitor to be coupled between the negative power line and an input terminal of the triggering unit. Thereby, the gate tunneling leakage is eliminated and the problem of mistriggering is prevented.
摘要翻译：提供了包括夹紧模块和检测模块的ESD保护电路。夹紧模块耦合在正电源线和负电源线之间。检测模块包括触发单元，电阻器和MOS电容器。触发单元的输出端子用于触发夹紧模块。电阻器耦合在负电源线和触发单元的输入端之间。 MOS电容器耦合在正电源线和用于ESD保护的触发单元的输入端子之间。在正常的电源操作期间，触发单元的开关端子使MOS电容器耦合在负电源线和触发单元的输入端之间。由此，消除了栅极隧道泄漏，并且防止了错误捕捉的问题。

5. 发明申请

US20090296295A1 Power-rail ESD protection circuit with ultra low gate leakage 有权
标题翻译：电源轨道ESD保护电路具有超低门极泄漏
公开(公告)号：US20090296295A1
公开(公告)日：2009-12-03
申请号：US12461237
申请日：2009-08-05
申请人： Ming-Dou Ker , Chin-Hao Chen , Ryan Hsin-Chin Jiang
发明人： Ming-Dou Ker , Chin-Hao Chen , Ryan Hsin-Chin Jiang
IPC分类号： H02H9/00
CPC分类号： H02H9/046
摘要： An ESD protection circuit including a clamping module and a detecting module is provided. The clamping module is coupled between a positive power line and a negative power line. The detecting module includes a triggering unit, a resistor, and a MOS capacitor. An output terminal of the triggering unit is used for triggering the clamping module. The resistor is coupled between the negative power line and an input terminal of the triggering unit. The MOS capacitor is coupled between the positive power line and an input terminal of the triggering unit for ESD protection. During a normal power operation, a switching terminal of the triggering unit enables the MOS capacitor to be coupled between the negative power line and an input terminal of the triggering unit. Thereby, the gate tunneling leakage is eliminated and the problem of mistriggering is prevented.
摘要翻译：提供了包括夹紧模块和检测模块的ESD保护电路。夹紧模块耦合在正电源线和负电源线之间。检测模块包括触发单元，电阻器和MOS电容器。触发单元的输出端子用于触发夹紧模块。电阻器耦合在负电源线和触发单元的输入端之间。 MOS电容器耦合在正电源线和用于ESD保护的触发单元的输入端子之间。在正常的电源操作期间，触发单元的开关端子使MOS电容器耦合在负电源线和触发单元的输入端之间。由此，消除了栅极隧道泄漏，并且防止了错误捕捉的问题。

6. 发明申请

US20090032837A1 ASYMMETRIC BIDIRECTIONAL SILICON-CONTROLLED RECTIFIER 有权
标题翻译：不对称双向硅控制整流器
公开(公告)号：US20090032837A1
公开(公告)日：2009-02-05
申请号：US12113410
申请日：2008-05-01
申请人： Tang-Kuei Tseng , Che-Hao Chuang , Ryan Hsin-Chin Jiang , Ming-Dou Ker
发明人： Tang-Kuei Tseng , Che-Hao Chuang , Ryan Hsin-Chin Jiang , Ming-Dou Ker
IPC分类号： H01L29/747
CPC分类号： H01L29/747 , H01L27/0262 , H01L29/87
摘要： The present invention discloses an asymmetric bidirectional silicon-controlled rectifier, which comprises: a second conduction type substrate; a first conduction type undoped epitaxial layer formed on the substrate; a first well and a second well both formed inside the undoped epitaxial layer and separated by a portion of the undoped epitaxial layer; a first buried layer formed in a junction between the first well and the substrate; a second buried layer formed in a junction between the second well and the substrate; a first and a second semiconductor area with opposite conduction type both formed inside the first well; a third and a fourth semiconductor area with opposite conduction type both formed inside the second well, wherein the first and second semiconductor areas are connected to the anode of the silicon-controlled rectifier, and the third and fourth semiconductor areas are connected to the cathode of the silicon-controlled rectifier.
摘要翻译：本发明公开了一种不对称双向硅控整流器，其包括：第二导电型衬底; 形成在基板上的第一导电型未掺杂外延层; 第一阱和第二阱都形成在未掺杂的外延层内部并由未掺杂的外延层的一部分分离; 第一掩埋层，形成在所述第一阱和所述衬底之间的接合处; 第二掩埋层，形成在所述第二阱和所述衬底之间的接合处; 在第一阱内形成具有相反导电类型的第一和第二半导体区域; 具有相反导电类型的第三和第四半导体区域都形成在第二阱内部，其中第一和第二半导体区域连接到可控硅整流器的阳极，并且第三和第四半导体区域连接到硅控整流器。

7. 发明申请

US20090021872A1 ESD protection circuit with active triggering 有权
标题翻译：具有主动触发的ESD保护电路
公开(公告)号：US20090021872A1
公开(公告)日：2009-01-22
申请号：US11826634
申请日：2007-07-17
申请人： Ming-Dou Ker , Yuan-Wen Hsiao , Ryan Hsin-Chin Jiang
发明人： Ming-Dou Ker , Yuan-Wen Hsiao , Ryan Hsin-Chin Jiang
IPC分类号： H02H3/22
CPC分类号： H01L27/0266 , H01L2924/0002 , H01L2924/00
摘要： An ESD protection circuit is provided. The circuit includes a discharging component, a diode, and an ESD detection circuit. The discharging component is coupled between an input/output pad and a first power line of an IC. The diode is coupled between the input/output pad and a second power line of the IC in a forward direction toward the second power line. The ESD detection circuit includes a capacitor, a resistor, and a triggering component. The capacitor and the resistor are formed in series and coupled between the first power line and the second power line. The triggering component has a positive power end coupled to the input/output pad and a negative power end coupled to the first power line. An input of the triggering component is coupled to a node between the capacitor and the resistor.
摘要翻译：提供ESD保护电路。电路包括放电元件，二极管和ESD检测电路。放电元件耦合在IC的输入/输出焊盘和第一电源线之间。所述二极管在所述输入/输出焊盘和所述IC的第二电源线之间朝向所述第二电力线向前方连接。 ESD检测电路包括电容器，电阻器和触发部件。电容器和电阻器串联形成并耦合在第一电源线和第二电源线之间。触发组件具有耦合到输入/输出焊盘的正功率端和耦合到第一电源线的负功率端。触发元件的输入耦合到电容器和电阻器之间的节点。

8. 发明授权

US08829775B2 Planar mirco-tube discharger structure and method for fabricating the same 有权
标题翻译：平面微管放电器结构及其制造方法
公开(公告)号：US08829775B2
公开(公告)日：2014-09-09
申请号：US13464506
申请日：2012-05-04
申请人： Tung-Yang Chen , Ming-Dou Ker , Ryan Hsin-Chin Jiang
发明人： Tung-Yang Chen , Ming-Dou Ker , Ryan Hsin-Chin Jiang
IPC分类号： H01J1/88 , H01J19/42 , H01J1/00 , H01J1/18
CPC分类号： H01J9/02 , H01J17/066
摘要： The present invention discloses a semiconductor-based planar micro-tube discharger structure and a method for fabricating the same. The method comprises steps: forming on a substrate two patterned electrodes separated by a gap and at least one separating block arranged in the gap; forming an insulating layer over the patterned electrodes and the separating block and filling the insulating layer into the gap. Thereby are formed at least two discharge paths. The method can fabricate a plurality discharge paths in a semiconductor structure. Therefore, the structure of the present invention has very high reliability and reusability.
摘要翻译：本发明公开了一种基于半导体的平面微管放电器结构及其制造方法。该方法包括以下步骤：在衬底上形成由间隙分开的两个图案化电极和布置在间隙中的至少一个分隔块; 在图案化电极和分离块上形成绝缘层，并将绝缘层填充到间隙中。由此形成至少两个排出路径。该方法可以在半导体结构中制造多个放电路径。因此，本发明的结构具有非常高的可靠性和可重用性。

9. 发明申请

US20130221834A1 PLANAR MIRCO-TUBE DISCHARGER STRUCTURE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：平面微管排放结构及其制造方法
公开(公告)号：US20130221834A1
公开(公告)日：2013-08-29
申请号：US13464506
申请日：2012-05-04
申请人： Tung-Yang Chen , Ming-Dou Ker , Ryan Hsin-Chin Jiang
发明人： Tung-Yang Chen , Ming-Dou Ker , Ryan Hsin-Chin Jiang
IPC分类号： H01J1/88 , C23C16/44 , B05D5/12
CPC分类号： H01J9/02 , H01J17/066
摘要： The present invention discloses a semiconductor-based planar micro-tube discharger structure and a method for fabricating the same. The method comprises steps: forming on a substrate two patterned electrodes separated by a gap and at least one separating block arranged in the gap; forming an insulating layer over the patterned electrodes and the separating block and filling the insulating layer into the gap. Thereby are formed at least two discharge paths. The method can fabricate a plurality discharge paths in a semiconductor structure. Therefore, the structure of the present invention has very high reliability and reusability.
摘要翻译：本发明公开了一种基于半导体的平面微管放电器结构及其制造方法。该方法包括以下步骤：在衬底上形成由间隙分开的两个图案化电极和布置在间隙中的至少一个分隔块; 在图案化电极和分离块上形成绝缘层，并将绝缘层填充到间隙中。由此形成至少两个排出路径。该方法可以在半导体结构中制造多个放电路径。因此，本发明的结构具有非常高的可靠性和可重用性。

10. 发明授权

US07915638B2 Symmetric bidirectional silicon-controlled rectifier 有权
标题翻译：对称双向硅控整流器
公开(公告)号：US07915638B2
公开(公告)日：2011-03-29
申请号：US12113912
申请日：2008-05-01
申请人： Tang-Kuei Tseng , Che-Hao Chuang , Ryan Hsin-Chin Jiang , Ming-Dou Ker
发明人： Tang-Kuei Tseng , Che-Hao Chuang , Ryan Hsin-Chin Jiang , Ming-Dou Ker
IPC分类号： H01L29/66
CPC分类号： H01L27/0262 , H01L29/747 , H01L29/87
摘要： The present invention discloses a symmetric bidirectional silicon-controlled rectifier, which comprises: a substrate; a buried layer formed on the substrate; a first well, a middle region and a second well, which are sequentially formed on the buried layer side-by-side; a first semiconductor area and a second semiconductor area both formed inside the first well; a third semiconductor area formed in a junction between the first well and the middle region, wherein a first gate is formed over a region between the second and third semiconductor areas; a fourth semiconductor area and a fifth semiconductor area both formed inside the second well; a sixth semiconductor area formed in a junction between the second well and the middle region, wherein a second gate is formed over a region between the fifth and sixth semiconductor areas.
摘要翻译：本发明公开了一种对称双向硅控整流器，其包括：衬底; 形成在基板上的掩埋层; 第一阱，中间区域和第二阱，并排地依次形成在掩埋层上; 第一半导体区域和第二半导体区域都形成在第一阱内; 形成在所述第一阱和所述中间区域之间的接合处的第三半导体区域，其中在所述第二和第三半导体区域之间的区域上形成第一栅极; 形成在第二阱内的第四半导体区域和第五半导体区域; 形成在所述第二阱和所述中间区域之间的接合处的第六半导体区域，其中在所述第五和第六半导体区域之间的区域上形成第二栅极。

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