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1. 发明授权

US09538582B2 Warpage control in the packaging of integrated circuits 有权
标题翻译：集成电路封装中的翘曲控制
公开(公告)号：US09538582B2
公开(公告)日：2017-01-03
申请号：US13559318
申请日：2012-07-26
申请人： Ming-Da Cheng , Hsiu-Jen Lin , Cheng-Ting Chen , Wei-Yu Chen , Chien-Wei Lee , Chung-Shi Liu
发明人： Ming-Da Cheng , Hsiu-Jen Lin , Cheng-Ting Chen , Wei-Yu Chen , Chien-Wei Lee , Chung-Shi Liu
IPC分类号： B23K31/02 , H01L21/00 , H05B3/02 , H01L21/677 , H01L21/683 , H01L23/00
CPC分类号： H05B3/02 , B23K3/087 , B23K2101/40 , H01L21/67721 , H01L21/6838 , H01L24/75 , H01L24/81 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/75744 , H01L2224/7598 , H01L2224/81191 , H01L2224/81815 , H01L2224/97 , H01L2924/3511 , H01L2924/37001 , Y10T29/41 , H01L2924/00014 , H01L2224/81 , H01L2924/014
摘要： A method includes placing a first package component over a vacuum boat, wherein the vacuum boat comprises a hole, and wherein the first package component covers the hole. A second package component is placed over the first package component, wherein solder regions are disposed between the first and the second package components. The hole is vacuumed, wherein the first package component is pressed by a pressure against the vacuum boat, and wherein the pressure is generated by a vacuum in the hole. When the vacuum in the hole is maintained, the solder regions are reflowed to bond the second package component to the first package component.
摘要翻译：一种方法包括将第一包装部件放置在真空舟皿上，其中真空舟皿包括孔，并且其中第一包装部件覆盖该孔。第二包装部件放置在第一包装部件上，其中焊料区域设置在第一和第二包装部件之间。该孔被抽真空，其中第一包装部件被压靠在真空舟皿上的压力，并且其中压力由孔中的真空产生。当保持孔中的真空时，回流焊接区域以将第二包装部件结合到第一包装部件。

2. 发明申请

US20140027431A1 Warpage Control in the Packaging of Integrated Circuits 有权
标题翻译：集成电路封装中的翘曲控制
公开(公告)号：US20140027431A1
公开(公告)日：2014-01-30
申请号：US13559318
申请日：2012-07-26
申请人： Ming-Da Cheng , Hsiu-Jen Lin , Cheng-Ting Chen , Wei-Yu Chen , Chien-Wei Lee , Chung-Shi Liu
发明人： Ming-Da Cheng , Hsiu-Jen Lin , Cheng-Ting Chen , Wei-Yu Chen , Chien-Wei Lee , Chung-Shi Liu
IPC分类号： B23K31/02 , H05B1/00 , B25B11/00
CPC分类号： H05B3/02 , B23K3/087 , B23K2101/40 , H01L21/67721 , H01L21/6838 , H01L24/75 , H01L24/81 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/75744 , H01L2224/7598 , H01L2224/81191 , H01L2224/81815 , H01L2224/97 , H01L2924/3511 , H01L2924/37001 , Y10T29/41 , H01L2924/00014 , H01L2224/81 , H01L2924/014
摘要： A method includes placing a first package component over a vacuum boat, wherein the vacuum boat comprises a hole, and wherein the first package component covers the hole. A second package component is placed over the first package component, wherein solder regions are disposed between the first and the second package components. The hole is vacuumed, wherein the first package component is pressed by a pressure against the vacuum boat, and wherein the pressure is generated by a vacuum in the hole. When the vacuum in the hole is maintained, the solder regions are reflowed to bond the second package component to the first package component.
摘要翻译：一种方法包括将第一包装部件放置在真空舟皿上，其中真空舟皿包括孔，并且其中第一包装部件覆盖该孔。第二包装部件放置在第一包装部件上，其中焊料区域设置在第一和第二包装部件之间。该孔被抽真空，其中第一包装部件被压靠在真空舟皿上的压力，并且其中压力由孔中的真空产生。当保持孔中的真空时，回流焊接区域以将第二包装部件结合到第一包装部件。

3. 发明申请

US20110148475A1 DRIVING CIRCUIT OF INPUT/OUTPUT INTERFACE 有权
标题翻译：输入/输出接口的驱动电路
公开(公告)号：US20110148475A1
公开(公告)日：2011-06-23
申请号：US12702016
申请日：2010-02-08
申请人： YU-TONG LIN , Yu-Chia Liu , Chien-Wei Lee
发明人： YU-TONG LIN , Yu-Chia Liu , Chien-Wei Lee
IPC分类号： G05F3/02
CPC分类号： H03K19/00361 , H03K5/1534 , H03K19/01721
摘要： A driving circuit of an input/output (I/O) interface is provided. The driving circuit includes a main output stage and an enhancing unit. The main output stage receives at least one driving signal and outputs an output signal corresponding to an input signal accordingly. The enhancing unit is coupled to the main output stage. The enhancing unit receives and detects the level of the output signal so as to drive the output force of the main output stage in a first output level or a second output level, wherein the first output level is higher than the second output level.
摘要翻译：提供输入/输出（I / O）接口的驱动电路。驱动电路包括主输出级和增强单元。主输出级接收至少一个驱动信号，并相应地输出与输入信号对应的输出信号。增强单元耦合到主输出级。增强单元接收并检测输出信号的电平，以驱动主输出级的输出力处于第一输出电平或第二输出电平，其中第一输出电平高于第二输出电平。

4. 发明申请

US20120223425A1 SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120223425A1
公开(公告)日：2012-09-06
申请号：US13105338
申请日：2011-05-11
申请人： Hui-Min Huang , Chun-Tang Lin , Chien-Wei Lee , Yen-Ping Wang
发明人： Hui-Min Huang , Chun-Tang Lin , Chien-Wei Lee , Yen-Ping Wang
IPC分类号： H01L23/498 , H01L21/768
CPC分类号： H01L23/522 , H01L23/481 , H01L24/05 , H01L24/13 , H01L2224/02372 , H01L2224/0401 , H01L2224/05548 , H01L2224/0557 , H01L2224/05572 , H01L2224/13022 , H01L2224/131 , H01L2924/00014 , H01L2224/05552
摘要： A semiconductor structure includes a chip, a plurality of metal posts disposed in the chip and a buffer layer disposed on the chip. The chip includes a silicon-based layer having opposite first and second surfaces, and a build-up structure formed on the first surface of the silicon-based layer consisting of at least a metal layer and a low-k dielectric layer alternatively stacked on one another. Each of the metal posts is disposed in the silicon-based layer with one end thereof electrically connected with the metal layer while the other end is exposed from the second surface of the silicon-based layer. The buffer layer is disposed on the build-up structure. By positioning the low-k dielectric layer far from the second surface that is used for connecting to an external electronic component, the present invention reduces the overall thermal stress.
摘要翻译：半导体结构包括芯片，设置在芯片中的多个金属柱和设置在芯片上的缓冲层。该芯片包括具有相对的第一和第二表面的硅基层，以及形成在硅基层的第一表面上的堆积结构，该硅基层至少由至少一层金属层和低k电介质层组成，另一个。每个金属柱设置在硅基层中，其一端与金属层电连接，而另一端从硅基层的第二表面露出。缓冲层设置在积聚结构上。通过将低k电介质层定位成远离用于连接到外部电子部件的第二表面，本发明降低了总的热应力。

5. 发明授权

US08603911B2 Semiconductor device and fabrication method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US08603911B2
公开(公告)日：2013-12-10
申请号：US13105338
申请日：2011-05-11
申请人： Hui-Min Huang , Chun-Tang Lin , Chien-Wei Lee , Yen-Ping Wang
发明人： Hui-Min Huang , Chun-Tang Lin , Chien-Wei Lee , Yen-Ping Wang
IPC分类号： H01L21/44 , H01L23/12 , H01L29/40
CPC分类号： H01L23/522 , H01L23/481 , H01L24/05 , H01L24/13 , H01L2224/02372 , H01L2224/0401 , H01L2224/05548 , H01L2224/0557 , H01L2224/05572 , H01L2224/13022 , H01L2224/131 , H01L2924/00014 , H01L2224/05552
摘要： A semiconductor structure includes a chip, a plurality of metal posts disposed in the chip and a buffer layer disposed on the chip. The chip includes a silicon-based layer having opposite first and second surfaces, and a build-up structure formed on the first surface of the silicon-based layer consisting of at least a metal layer and a low-k dielectric layer alternatively stacked on one another. Each of the metal posts is disposed in the silicon-based layer with one end thereof electrically connected with the metal layer while the other end is exposed from the second surface of the silicon-based layer. The buffer layer is disposed on the build-up structure. By positioning the low-k dielectric layer far from the second surface that is used for connecting to an external electronic component, the present invention reduces the overall thermal stress.
摘要翻译：半导体结构包括芯片，设置在芯片中的多个金属柱和设置在芯片上的缓冲层。该芯片包括具有相对的第一和第二表面的硅基层，以及形成在硅基层的第一表面上的堆积结构，该硅基层至少由至少一层金属层和低k电介质层组成，另一个。每个金属柱设置在硅基层中，其一端与金属层电连接，而另一端从硅基层的第二表面露出。缓冲层设置在积聚结构上。通过将低k电介质层定位成远离用于连接到外部电子部件的第二表面，本发明降低了总的热应力。

6. 发明申请

US20100326644A1 Plane-type heat-dissipating structure with high heat-dissipating effect and method for manufacturing the same 审中-公开
标题翻译：具有高散热效果的平面型散热结构及其制造方法
公开(公告)号：US20100326644A1
公开(公告)日：2010-12-30
申请号：US12458037
申请日：2009-06-30
申请人： Shui-Hsu Hung , Chien-Wei Lee , Shih-Wei Lee
发明人： Shui-Hsu Hung , Chien-Wei Lee , Shih-Wei Lee
IPC分类号： F28F3/04 , B21D53/02
CPC分类号： F28D15/0233 , F28D15/0283 , F28D15/046 , F28D2021/0029 , F28F1/42 , F28F1/422 , F28F13/187 , F28F2275/14 , H01L23/427 , H01L2924/0002 , Y10T29/4935 , H01L2924/00
摘要： A plane-type heat-dissipating structure with high heat-dissipating effect includes a first heat-dissipating unit and a second heat-dissipating unit. The first heat-dissipating unit has an evacuated hollow heat-dissipating body, a plurality of supports integratedly formed in the hollow heat-dissipating body in order to divide an inner space of the hollow heat-dissipating body into a plurality of receiving spaces, and a plurality of microstructures integratedly formed on an inner surface of the hollow heat-dissipating body. Work liquid is filled into the receiving spaces. The second heat-dissipating unit is integratedly formed on an outer surface of the first heat-dissipating unit.
摘要翻译：具有高散热效果的平面型散热结构包括第一散热单元和第二散热单元。第一散热单元具有抽真空的中空散热体，多个支撑件，整体地形成在中空散热体中，以便将中空散热体的内部空间分成多个接收空间，以及多个微结构整体地形成在中空散热体的内表面上。工作液体填充到收容空间。第二散热单元一体地形成在第一散热单元的外表面上。

7. 发明申请

US20060288914A1 Compound pallet 审中-公开
标题翻译：复合托盘
公开(公告)号：US20060288914A1
公开(公告)日：2006-12-28
申请号：US11167732
申请日：2005-06-28
申请人： Chien-Wei Lee
发明人： Chien-Wei Lee
IPC分类号： B65D19/00
CPC分类号： B65D19/0038 , B65D19/40 , B65D2519/00039 , B65D2519/00074 , B65D2519/00273 , B65D2519/00278 , B65D2519/00288 , B65D2519/00318 , B65D2519/00333 , Y02W90/11
摘要： A compound pallet comprising an upper compound plate and a lower compound plate; each plate being formed by using a plurality of plate layers clamping a plurality of fiber layers; and filling material is filled between the plate fibers and the fiber layers; and the filling material being formed by 35 to 40 neutral liquid, 5 to 10% of adhesive, 40% of cement and 20% of edible seaweed. The upper compound plate is formed with a plurality of protruded ribs so that a cross section of the upper compound plate is formed as continuous rectangular waves; and the lower compound plate is formed with a plurality of protruded ribs so that a cross section of the lower compound plate is formed as continuous rectangular waves; and the orientation of the ribs of the upper compound plate is vertical to the orientation of the ribs of the lower compound plate.
摘要翻译：复合托盘，包括上复合板和下复合板; 每个板通过使用夹持多个纤维层的多个板层形成; 并且填充材料填充在板状纤维和纤维层之间; 填充材料由35-40个中性液体，5至10％的粘合剂，40％的水泥和20％的可食用海藻形成。上复合板形成有多个突出的肋，使得上复合板的横截面形成为连续的矩形波; 并且下复合板形成有多个凸肋，使得下复合板的横截面形成为连续的矩形波; 并且上复合板的肋的取向垂直于下复合板的肋的取向。

8. 发明授权

US08130013B2 Driving circuit of input/output interface with changeable output force 有权
标题翻译：具有可变输出力的输入/输出接口的驱动电路
公开(公告)号：US08130013B2
公开(公告)日：2012-03-06
申请号：US12702016
申请日：2010-02-08
申请人： Yu-Tong Lin , Yu-Chia Liu , Chien-Wei Lee
发明人： Yu-Tong Lin , Yu-Chia Liu , Chien-Wei Lee
IPC分类号： H03K3/00
CPC分类号： H03K19/00361 , H03K5/1534 , H03K19/01721
摘要： A driving circuit of an input/output (I/O) interface is provided. The driving circuit includes a main output stage and an enhancing unit. The main output stage receives at least one driving signal and outputs an output signal corresponding to an input signal accordingly. The enhancing unit is coupled to the main output stage. The enhancing unit receives and detects the level of the output signal so as to drive the output force of the main output stage in a first output level or a second output level, wherein the first output level is higher than the second output level.
摘要翻译：提供输入/输出（I / O）接口的驱动电路。驱动电路包括主输出级和增强单元。主输出级接收至少一个驱动信号，并相应地输出与输入信号对应的输出信号。增强单元耦合到主输出级。增强单元接收并检测输出信号的电平，以驱动主输出级的输出力处于第一输出电平或第二输出电平，其中第一输出电平高于第二输出电平。

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