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1. 发明授权

US06794308B2 Method for reducing by-product deposition in wafer processing equipment 有权
标题翻译：降低晶片加工设备中副产物沉积的方法
公开(公告)号：US06794308B2
公开(公告)日：2004-09-21
申请号：US09727547
申请日：2000-12-04
申请人： Ming Jang Hwang , Keizo Hosoda , Shintaro Aoyama , Tadashi Terasaki , Tsuyoshi Tamaru
发明人： Ming Jang Hwang , Keizo Hosoda , Shintaro Aoyama , Tadashi Terasaki , Tsuyoshi Tamaru
IPC分类号： H01L2131
CPC分类号： C23C16/45519 , C23C16/4401 , C23C16/4412 , C23C16/45521 , C23C16/4557 , C23C16/4558
摘要： A method of reducing by-product deposition inside wafer processing equipment includes providing a chamber having a peripheral inner wall and placing a semiconductor wafer within the chamber. The method also includes placing a ring within the chamber proximate the peripheral inner wall and introducing a plurality of reactant gases into the chamber and reacting the gases. The method also includes introducing a heated gas into the chamber through the ring proximate the peripheral inner wall to increase the temperature of the peripheral inner wall.
摘要翻译：减少晶片处理设备内的副产物沉积的方法包括提供具有周边内壁并将半导体晶片放置在室内的室。该方法还包括将腔环放置在邻近周边内壁的腔室内，并将多个反应气体引入腔室并使气体反应。该方法还包括通过靠近周围内壁的环将加热的气体引入室中，以增加周边内壁的温度。

2. 发明授权

US06730613B1 Method for reducing by-product deposition in wafer processing equipment 有权
公开(公告)号：US06730613B1
公开(公告)日：2004-05-04
申请号：US09354459
申请日：1999-07-15
申请人： Ming Jang Hwang , Keizo Hosoda , Shintaro Aoyama , Tadashi Terasaki , Tsuyoshi Tamaru
发明人： Ming Jang Hwang , Keizo Hosoda , Shintaro Aoyama , Tadashi Terasaki , Tsuyoshi Tamaru
IPC分类号： H01L2131
CPC分类号： C23C16/45521 , C23C16/4401 , C23C16/4412 , C23C16/4557 , C23C16/4558
摘要： A method of reducing by-product deposition inside wafer processing equipment includes providing a chamber having a peripheral inner wall and placing a semiconductor wafer within the chamber. The method also includes placing a ring within the chamber proximate the peripheral inner wall and introducing a plurality of reactant gases into the chamber and reacting the gases. The method also includes introducing a heated gas into the chamber through the ring proximate the peripheral inner wall to increase the temperature of the peripheral inner wall.

3. 发明授权

US06214710B1 Method for a semiconductor device having reduced contact resistance and leakage 有权
标题翻译：具有降低的接触电阻和泄漏的半导体器件的方法
公开(公告)号：US06214710B1
公开(公告)日：2001-04-10
申请号：US09207088
申请日：1998-12-07
申请人： Kyung-Ho Park , Chih-Chen Cho , Ming Jang Hwang
发明人： Kyung-Ho Park , Chih-Chen Cho , Ming Jang Hwang
IPC分类号： H01L213205
CPC分类号： H01L29/665 , H01L21/28052 , H01L21/28518
摘要： A method of forming a semiconductor device includes separating a semiconductor gate body from the outer surface of the substrate by a gate insulator layer, forming a conductive drain region in the outer surface of the substrate and spaced apart from the gate conductor body, and forming a conductive source region in the outer surface of the substrate and spaced apart from the gate conductor body opposite the conductive drain region to define a channel region in the substrate disposed inwardly from the gate body and the gate insulator layer. The method also includes depositing a metal buffer layer over the conductive source region and conductive drain region, depositing a metal layer over the metal buffer layer, and reacting the metal layer and metal buffer layer with the conductive source region and conductive drain region to form respective first and second silicide regions.
摘要翻译：形成半导体器件的方法包括：通过栅极绝缘体层将半导体栅极本体与衬底的外表面分离，在衬底的外表面中形成导电漏区，并与栅极导体本体间隔开，形成导电源区域，并且与栅极导体本体相对的导电漏极区域隔开，以限定衬底中的沟道区，该沟道区域从栅极本体和栅极绝缘体层向内设置。该方法还包括在导电源区和导电漏极区上沉积金属缓冲层，在金属缓冲层上沉积金属层，并使金属层和金属缓冲层与导电源区和导电漏区反应形成相应的第一和第二硅化物区域。

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