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1. 发明授权

US5140401A CMOS ESD protection circuit with parasitic SCR structures 失效
标题翻译：具有寄生SCR结构的CMOS ESD保护电路
公开(公告)号：US5140401A
公开(公告)日：1992-08-18
申请号：US674666
申请日：1991-03-25
申请人： Ming D. Ker , Chung Y. Lee , Chung Y. Wu , Joe Ko
发明人： Ming D. Ker , Chung Y. Lee , Chung Y. Wu , Joe Ko
IPC分类号： H01L27/02
CPC分类号： H01L27/0251
摘要： A circuit for protecting a CMOS device against execssive voltages has two SCR circuits in which the bipolar transistors are formed as parasitic devices. One SCR circuit is connected between a line to be protected and one power supply point and the other SCR circuit is connected between the line to be protected and the other power supply point. The power supply points form sinks for currents associated with excessive voltages, and they form reference potential points for establishing the voltage at which an SCR turns on. A semiconductor device having an n-substrate has three p-wells. The center p-well (as seen in section) forms part of two vertical transistors, one for each of the two SCR's. Each outer p-well cooperates with the center p-well and the intervening substrate to form a lateral transistor for one of the SCR's. These transistors use shared semiconductor regions that establish the base to collector interconnections of an SCR. These regions and other structures also form an FET and a diode in each SCR circuit that turn on the SCR in response to an excessive voltage.
摘要翻译：用于保护CMOS器件免受执行电压的电路具有两个SCR电路，其中双极晶体管形成为寄生器件。一个SCR电路连接在要保护的线路和一个电源点之间，另一个SCR电路连接在要保护的线路和另一个电源点之间。电源点形成与过电压相关的电流的吸收点，并且它们形成用于建立SCR导通的电压的参考电位点。具有n衬底的半导体器件具有三个p阱。中心p阱（如部分所示）构成两个垂直晶体管的一部分，一个用于两个SCR的每一个。每个外部p阱与中心p阱和中间衬底配合以形成用于SCR之一的横向晶体管。这些晶体管使用建立SCR的基极到集电极互连的共享半导体区域。这些区域和其他结构还在每个SCR电路中形成FET和二极管，以响应于过高的电压而导通SCR。

2. 发明授权

US5821629A Buried structure SRAM cell and methods for fabrication 失效
标题翻译：埋地结构SRAM单元及其制造方法
公开(公告)号：US5821629A
公开(公告)日：1998-10-13
申请号：US501711
申请日：1995-07-12
申请人： Jemmy Wen , Joe Ko
发明人： Jemmy Wen , Joe Ko
IPC分类号： H01L21/76 , H01L21/762 , H01L21/8244 , H01L27/11
CPC分类号： H01L27/1112 , H01L21/76 , H01L21/76202 , H01L27/11 , Y10S257/904
摘要： An improved SRAM cell having ultra-high density and methods for fabrication are described. Each SRAM cell, according to the present invention, has its own buried structure, including word lines (i.e., gate regions) and bit lines (i.e., source/drain regions), thus increasing the cell ratio of channel width of cell transistor to that of pass transistor to keep the data stored in the cell transistor more stable without increasing the area per cell. In addition, according to the present invention, the field isolation between active regions is not field oxide but blankly ion-implanted silicon substrate. Therefore, SRAM cells can be densely integrated due to the absence of bird's beak encroachment. Since the present invention has more planar topography than the prior art, it is easily adapted to the VLSI process, which is always restricted by the limit of resolution of photolithography, thus increasing the degree of integration.
摘要翻译：描述了具有超高密度的改进的SRAM单元和制造方法。根据本发明的每个SRAM单元具有其自己的掩埋结构，包括字线（即，栅极区）和位线（即，源极/漏极区），从而将单元晶体管的沟道宽度的单元比增加到的传输晶体管，以保持存储在单元晶体管中的数据更稳定，而不增加每个单元的面积。此外，根据本发明，有源区之间的场隔离不是场氧化物而是空心离子注入的硅衬底。因此，由于没有鸟喙侵入，SRAM单元可以密集地集成。由于本发明具有比现有技术更平坦的形貌，所以易于适应于VLSI工艺，VLSI工艺总是受到光刻分辨率的限制，从而增加了集成度。

3. 发明授权

US5686321A Local punchthrough stop for ultra large scale integration devices 失效
标题翻译：超大规模集成设备的本地突破
公开(公告)号：US5686321A
公开(公告)日：1997-11-11
申请号：US647266
申请日：1996-05-06
申请人： Joe Ko , Chih-Hung Lin
发明人： Joe Ko , Chih-Hung Lin
IPC分类号： H01L21/336 , H01L29/10 , H01L29/78 , H01L21/265
CPC分类号： H01L29/66583 , H01L29/1083 , H01L29/66537 , H01L29/66553 , H01L29/7833
摘要： The invention relates to an improved MOSFET device structure for use in ultra large scale integration and the method of forming the device structure. A local punchthrough stop region is formed directly under the gate electrode using ion implantation. The local punchthrough stop region reduces the expansion of the depletion region in the channel and thereby increases the punchthrough voltage. The local punchthrough stop region is self-aligned with the gate electrode and source/drain region so that critical spacings are maintained even for sub micron devices. The source and drain junction capacitances are also reduced. The invention can be used in either N channel or P channel MOSFET devices. The invention can be used with a conventional source/drain structure as well as a double doped drain structure and a light doped drain structure.
摘要翻译：本发明涉及用于超大规模集成的改进的MOSFET器件结构以及形成器件结构的方法。使用离子注入在栅电极正下方形成局部穿通停止区域。局部穿通停止区域减小了通道中耗尽区的扩展，从而增加了穿透电压。局部穿通停止区域与栅极电极和源极/漏极区域自对准，使得即使对于亚微米器件也保持临界间隔。源极和漏极结电容也减小。本发明可用于N沟道或P沟道MOSFET器件。本发明可以与传统的源极/漏极结构以及双掺杂漏极结构和掺杂掺杂的漏极结构一起使用。

4. 发明授权

US5518941A Maskless method for formation of a field implant channel stop region 失效
标题翻译：用于形成场注入通道停止区域的无掩模方法
公开(公告)号：US5518941A
公开(公告)日：1996-05-21
申请号：US312122
申请日：1994-09-26
申请人： Chih-Hung Lin , Joe Ko
发明人： Chih-Hung Lin , Joe Ko
IPC分类号： H01L21/336 , H01L21/762 , H01L21/265
CPC分类号： H01L29/6659 , H01L21/76202
摘要： This invention provides a method of forming a field implant channel stop region and a device using a field implant channel stop region to improve isolation between devices in integrated circuits using field effect transistors. The field implant channel stop region is formed without the use of an extra mask or extra masking steps by means of either a large angle tilted ion implant beam or a higher energy normally directed ion implant beam. The field implant channel stop region is formed with the mask used to form the light doped drain region in place. The field implant channel stop region forms a local increase in the doping level in the device well thereby forming the channel stop region.
摘要翻译：本发明提供一种形成场注入通道停止区域的方法和使用场注入通道停止区域的装置，以改善使用场效应晶体管的集成电路中的器件之间的隔离。通过大角度倾斜离子注入光束或较高能量的正向定向离子注入光束，形成场注入通道停止区域，而不需要使用额外的掩模或额外的掩模步骤。场用注入沟道阻挡区域形成有用于在适当位置形成光掺杂漏极区域的掩模。场注入沟道停止区域在器件阱中形成掺杂水平的局部增加，从而形成沟道停止区域。

5. 发明授权

US5393693A "Bird-beak-less" field isolation method 失效
标题翻译： “无鸟”现场隔离方法
公开(公告)号：US5393693A
公开(公告)日：1995-02-28
申请号：US254533
申请日：1994-06-06
申请人： Joe Ko , Chih-Hung Lin
发明人： Joe Ko , Chih-Hung Lin
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/7621 , H01L21/76213
摘要： A method of forming field oxide isolation regions for submicron technology using oxygen implantation is described. A first insulating layer is formed over a silicon substrate. A second insulating layer is formed over the first insulating layer. A first opening is formed in the first and second insulating layers. Sidewall spacers are formed on the vertical surfaces of the first and second insulating layers, within the first opening, to define a second, smaller opening. A portion of the silicon substrate is removed in the region defined by the second, smaller opening, to form an etched region of the silicon substrate. The sidewall spacers are removed. Oxygen is implanted into the etched region of the silicon substrate and into the region of the silicon substrate under the former location of the sidewall spacers. A portion of the polycrystalline silicon in and above the etched region of the silicon substrate. The field oxide isolation region is formed by heating. The remainder of the first and second insulating layers are removed.
摘要翻译：描述了使用氧气注入形成亚微米技术的场氧化物隔离区域的方法。在硅衬底上形成第一绝缘层。在第一绝缘层上形成第二绝缘层。在第一和第二绝缘层中形成第一开口。在第一开口内的第一和第二绝缘层的垂直表面上形成侧壁间隔物，以限定第二较小的开口。在由第二较小开口限定的区域中去除硅衬底的一部分，以形成硅衬底的蚀刻区域。去除侧壁间隔物。将氧气注入到硅衬底的蚀刻区域中并进入硅衬底的位于侧壁间隔物的前面位置的区域中。在硅衬底的蚀刻区域内和上方的多晶硅的一部分。通过加热形成场氧化物隔离区域。去除第一和第二绝缘层的其余部分。

6. 发明授权

US06555893B1 Bar circuit for an integrated circuit 有权
标题翻译：集成电路的棒电路
公开(公告)号：US06555893B1
公开(公告)日：2003-04-29
申请号：US10054934
申请日：2002-01-25
申请人： David Cheng-Hsiung Chen , Joe Ko
发明人： David Cheng-Hsiung Chen , Joe Ko
IPC分类号： H01L2900
CPC分类号： H01L23/5227 , H01L21/761 , H01L23/5222 , H01L27/08 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： The present invention provides a bar circuit for reducing cross talk and eddy current of an integrated circuit. The bar circuit comprises a semiconductor substrate with a first conductivity type; a strip of first well with a second conductivity type in the semiconductor substrate; and a strip of second well with the second conductivity type in the semiconductor substrate. The strip of second well is located below and adjacent to the strip of first well, whereby forms a junction barrier for reducing the cross talk and the eddy current.
摘要翻译：本发明提供一种用于减少集成电路的串扰和涡电流的条形电路。棒电路包括具有第一导电类型的半导体衬底; 在半导体衬底中具有第二导电类型的第一阱条; 以及在半导体衬底中具有第二导电类型的第二阱条。第二井的条带位于第一井的下方并且邻近第一井的条带，由此形成用于减少串扰和涡流的连接屏障。

7. 发明授权

US06207535B1 Method of forming shallow trench isolation 失效
标题翻译：形成浅沟槽隔离的方法
公开(公告)号：US06207535B1
公开(公告)日：2001-03-27
申请号：US09531903
申请日：2000-03-20
申请人： Kan-Yuan Lee , Joe Ko , Yang-Hui Fang , Gary Hong
发明人： Kan-Yuan Lee , Joe Ko , Yang-Hui Fang , Gary Hong
IPC分类号： H01L2176
CPC分类号： H01L21/76224 , Y10S148/05
摘要： A method of fabricating shallow trench isolations (STI) which forms a substrate with a patterned first oxide layer and a patterned silicon nitride layer thereon, so that active regions are defined with openings formed between the active regions. The openings are then over etched to form trenches for fabricating the STI, followed by forming a second oxide layer that conforms to a profile of the trenches. A third oxide layer is globally formed over the second oxide layer, sidewalls of the first oxide layer, and the silicon nitride layer. A thermal process is performed to densify a portion of the third oxide layer, so that a top portion of the third oxide layer is harder than a lower portion of the third oxide layer. The excessive portion of the third oxide layer above the silicon nitride layer is removed by performing chemical mechanical polishing, which planarizes a top surface of the third oxide layer in order to complete the manufacture of the STI.
摘要翻译：制造浅沟槽隔离（STI）的方法，其形成具有图案化的第一氧化物层和其上的图案化氮化硅层的衬底，使得有源区域被限定为在有源区域之间形成的开口。然后将这些开口过蚀刻以形成用于制造STI的沟槽，随后形成符合沟槽轮廓的第二氧化物层。在第二氧化物层，第一氧化物层的侧壁和氮化硅层上全局形成第三氧化物层。执行热处理以使第三氧化物层的一部分致密化，使得第三氧化物层的顶部比第三氧化物层的下部更硬。通过进行化学机械抛光来去除氮化硅层上方的第三氧化物层的过剩部分，其平坦化第三氧化物层的顶表面以完成STI的制造。

8. 发明授权

US06194271B1 Method for fabricating flash memory 有权
标题翻译：制造闪存的方法
公开(公告)号：US06194271B1
公开(公告)日：2001-02-27
申请号：US09237295
申请日：1999-01-25
申请人： Chih-Hung Lin , Joe Ko
发明人： Chih-Hung Lin , Joe Ko
IPC分类号： H01L218247
CPC分类号： H01L27/11521
摘要： A method of fabricating a flash memory. A gate is formed on a provided substrate. A first doping process is performed. A patterned mask layer is formed over the substrate. A shallow trench isolation structure is formed in the substrate by using the gate and the mask layer as a mask. A portion of the substrate defined below the gate is a first active region and a portion of the substrate defined below the mask layer is a second active region. The mask layer is removed. A dielectric layer and a conductive layer are formed in sequence over the substrate. The conductive layer, the dielectric layer and the gate are patterned to form a control gate and a floating gate, wherein a portion of the control gate overlap with the second active region. A second doping process is performed.
摘要翻译：一种制造闪速存储器的方法。栅极形成在所提供的衬底上。执行第一掺杂过程。在衬底上形成图案化掩模层。通过使用栅极和掩模层作为掩模在衬底中形成浅沟槽隔离结构。位于栅极下方的衬底的一部分是第一有源区，并且限定在掩模层下面的衬底的一部分是第二有源区。去除掩模层。在衬底上依次形成电介质层和导电层。将导电层，电介质层和栅极图案化以形成控制栅极和浮置栅极，其中控制栅极的一部分与第二有源区域重叠。执行第二掺杂过程。

9. 发明授权

US6159803A Method of fabricating flash memory 有权
标题翻译：制造闪存的方法
公开(公告)号：US6159803A
公开(公告)日：2000-12-12
申请号：US186404
申请日：1998-11-04
申请人： Gary Hong , Joe Ko
发明人： Gary Hong , Joe Ko
IPC分类号： H01L21/336 , H01L21/8247
CPC分类号： H01L29/66825
摘要： A method of fabicrating a flash memory. A semiconductor substrate having a field oxide layer which comprises a plurality of parallel oxide lines, a plurality of parallel word lines perpendicular to the parallel oxide lines, a dielectric layer having a same structure as and under the word lines, a plurality of floating gates separated by the field oxide layer from each other under the dielectric layer, and a plurality of regions encompassed by the field oxide laver and the word lines is provided. A first step of ion implantation to the substrate is performed by using the word lines as masks, so that a plurality of source regions and a plurality of drain regions are formed beside the word lines. Whereas each of the source regions and each of the drain regions are formed in the regions encompassed by the field oxide layer and the word lines. A photo-resist layer is formed to cover the drain regions. A second step of ion implantation to the substrate is performed by using the photo-resist layer and the parallel word lines as masks. The photo-resist layer is removed.
摘要翻译：闪存的方法。一种具有场氧化物层的半导体衬底，其包括多个平行氧化物线，垂直于所述平行氧化物线的多条平行字线，与所述字线具有相同结构的电介质层，分隔开的多个浮动栅极通过电介质层下的场氧化物层，并且提供由场氧化物紫菜和字线包围的多个区域。通过使用字线作为掩模来进行离子注入到衬底的第一步骤，使得在字线旁边形成多个源极区域和多个漏极区域。而源极区域和漏极区域中的每一个形成在由场氧化物层和字线包围的区域中。形成覆盖漏区的光刻胶层。通过使用光致抗蚀剂层和平行字线作为掩模来进行离子注入到衬底的第二步骤。除去光致抗蚀剂层。

10. 发明授权

US5817577A Grounding method for eliminating process antenna effect 失效
标题翻译：消除工艺天线效应的接地方法
公开(公告)号：US5817577A
公开(公告)日：1998-10-06
申请号：US746068
申请日：1996-11-05
申请人： Joe Ko
发明人： Joe Ko
IPC分类号： H01L27/02 , H01L21/443
CPC分类号： H01L27/0251 , H01L24/06 , H01L2224/02166 , H01L2924/14
摘要： A method for eliminating the antenna effect in the manufacture of an integrated circuit in a silicon substrate, wherein there are contact pad areas at the periphery of the integrated circuit and interconnection lines connecting the contact pad areas with the integrated circuit. This is achieved by grounding the contact pad areas to the silicon substrate; processing in a plasma environment that would normally produce electrical charge build-up at the gate oxide of the integrated circuit, but wherein the grounded contact pad areas eliminates the charge build-up; and disabling the grounding of the contact pad areas to retrieve the functioning of the integrated circuit.
摘要翻译：一种用于消除在硅衬底中制造集成电路中的天线效应的方法，其中在集成电路的周围存在接触焊盘区域和将接触焊盘区域与集成电路连接的互连线。这通过将接触焊盘区域接地到硅衬底来实现; 在等离子体环境中的处理，其通常会在集成电路的栅极氧化物处产生电荷积累，但是其中接地接触焊盘区域消除了电荷积聚; 并禁用接触焊盘区域的接地以检索集成电路的功能。

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