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1. 发明申请

US20060049851A1 Integrated circuit devices having data inversion circuits therein with multi-bit prefetch structures and methods of operating same 有权
标题翻译：具有其中具有多位预取结构的数据反转电路的集成电路器件及其操作方法
公开(公告)号：US20060049851A1
公开(公告)日：2006-03-09
申请号：US11266581
申请日：2005-11-03
申请人： Min-sang Park , Jin-seok Kwak , Seong-jin Jang
发明人： Min-sang Park , Jin-seok Kwak , Seong-jin Jang
IPC分类号： H03K19/094
CPC分类号： H03K19/00346
摘要： Integrated circuit devices include data inversion circuits therein that are configured to evaluate at least first and second ordered groups of input data in parallel with an ordered group of output data previously generated by the data inversion circuit. The data inversion circuit is further configured to generate inverted versions of the first and second ordered groups of input data as versions of the first and second ordered groups of data in parallel at outputs thereof whenever a number of bit differences between the first ordered group of input data and the ordered group of output data is greater than one-half a size of the first ordered group of input data and a number of bit differences between the second ordered group of input data and the version of the first ordered group of input data is greater than one-half a size of the second ordered group of input data, respectively.
摘要翻译：集成电路装置包括其中的数据反转电路，其被配置为与由数据反相电路预先产生的有序输出数据组并行地评估至少第一和第二有序输入数据组。数据反转电路还被配置为当输入的第一和第二有序组数据的第一有序组合的数量与第一有序数组组的输入数据和有序的输出数据组大于输入数据的第一个有序组的大小的一半，输入数据的第二个有序组与输入数据的第一个有序组的版本之间的位数差异为分别大于二阶输入数据组的二分之一。

2. 发明授权

US06992506B2 Integrated circuit devices having data inversion circuits therein with multi-bit prefetch structures and methods of operating same 有权
公开(公告)号：US06992506B2
公开(公告)日：2006-01-31
申请号：US10815505
申请日：2004-04-01
申请人： Min-sang Park , Jin-seok Kwak , Seong-jin Jang
发明人： Min-sang Park , Jin-seok Kwak , Seong-jin Jang
IPC分类号： G06F7/50 , G06F11/00 , H03K19/21 , H03M13/00
CPC分类号： H03K19/00346
摘要： Integrated circuit devices include data inversion circuits therein that are configured to evaluate at least first and second ordered groups of input data in parallel with an ordered group of output data previously generated by the data inversion circuit. The data inversion circuit is further configured to generate inverted versions of the first and second ordered groups of input data as versions of the first and second ordered groups of data in parallel at outputs thereof whenever a number of bit differences between the first ordered group of input data and the ordered group of output data is greater than one-half a size of the first ordered group of input data and a number of bit differences between the second ordered group of input data and the version of the first ordered group of input data is greater than one-half a size of the second ordered group of input data, respectively.

3. 发明授权

US07408482B2 Integrated circuit devices having data inversion circuits therein with multi-bit prefetch structures and methods of operating same 有权
标题翻译：具有其中具有多位预取结构的数据反转电路的集成电路器件及其操作方法
公开(公告)号：US07408482B2
公开(公告)日：2008-08-05
申请号：US11266581
申请日：2005-11-03
申请人： Min-sang Park , Jin-seok Kwak , Seong-jin Jang
发明人： Min-sang Park , Jin-seok Kwak , Seong-jin Jang
IPC分类号： H03M5/00
CPC分类号： H03K19/00346
摘要： Integrated circuit devices include data inversion circuits therein that are configured to evaluate at least first and second ordered groups of input data in parallel with an ordered group of output data previously generated by the data inversion circuit. The data inversion circuit is further configured to generate inverted versions of the first and second ordered groups of input data as versions of the first and second ordered groups of data in parallel at outputs thereof whenever a number of bit differences between the first ordered group of input data and the ordered group of output data is greater than one-half a size of the first ordered group of input data and a number of bit differences between the second ordered group of input data and the version of the first ordered group of input data is greater than one-half a size of the second ordered group of input data, respectively.
摘要翻译：集成电路装置包括其中的数据反转电路，其被配置为与由数据反相电路预先产生的有序输出数据组并行地评估至少第一和第二有序输入数据组。数据反转电路还被配置为当输入的第一和第二有序组数据的第一有序组合的数量与第一有序数组组的输入数据和有序的输出数据组大于输入数据的第一个有序组的大小的一半，输入数据的第二个有序组与输入数据的第一个有序组的版本之间的位数差异为分别大于二阶输入数据组的二分之一。

4. 发明申请

US20050127945A1 Data inversion circuits having a bypass mode of operation and methods of operating the same 有权
标题翻译：具有旁路操作模式的数据反转电路及其操作方法
公开(公告)号：US20050127945A1
公开(公告)日：2005-06-16
申请号：US10991076
申请日：2004-11-17
申请人： Min-sang Park
发明人： Min-sang Park
IPC分类号： G11C7/10 , H03K19/003 , H03K19/21
CPC分类号： H03K19/00346 , H03K19/00361
摘要： An integrated circuit device includes a data inversion circuit configured to support an inversion mode of operation. The inversion mode of operation inverts selected ones of a plurality of N-bit words received in consecutive sequence at inputs thereof. The data inversion circuit is further configured to support a bypass mode of operation. The bypass mode of operation disables inversion of a second one of the plurality of N-bit words when a delay between receipt of the second one of the plurality of N-bit words and receipt of an immediately preceding first one of the plurality of N-bit words is greater than a predetermined time interval. Related methods are also discussed.
摘要翻译：集成电路装置包括配置为支持反转操作模式的数据反转电路。反转操作模式反转在其输入处以连续顺序接收的多个N位字中选定的一个。数据反转电路还被配置为支持旁路操作模式。旁路操作模式在接收到多个N位字中的第二个N位字之间的延迟和接收多个N位字之中的前一个第一个之前的第一个N位字时，位字大于预定时间间隔。还讨论了相关方法。

5. 发明授权

US06323693B1 Current sense amplifier circuit using dummy bit line 有权
标题翻译：电流检测放大器电路采用虚拟位线
公开(公告)号：US06323693B1
公开(公告)日：2001-11-27
申请号：US09632459
申请日：2000-08-04
申请人： Min-sang Park
发明人： Min-sang Park
IPC分类号： G11C706
CPC分类号： G11C7/14 , G11C7/062 , G11C7/067 , G11C2207/063
摘要： A current sense amplifier circuit using a dummy bit line is provided. The current sense amplifier circuit includes a cell current generator, a reference current generator, and a sense amplifier. The cell current generator includes a memory cell connected to a word line and a bit line and generates memory cell current applied to the memory cell and bit line charge current for charging the bit line. The reference current generator includes a dummy bit line and a reference cell and generates reference cell current applied to the reference cell and dummy bit line charge current for charging the dummy bit line. The sense amplifier includes a first input terminal, connected to the cell current generator, for receiving the memory cell current and the bit line charge current and a second input terminal, connected to the reference current generator, for receiving the reference cell current and the dummy bit line charge current. The sense amplifier senses and amplifies the difference between current applied through the first input terminal and current applied through the second input terminal. The current sense amplifier circuit senses data at high speed regardless of the bit line charge current in the case of a turned-off cell and has a symmetric structure for stable operation.
摘要翻译：提供了使用虚拟位线的电流读出放大器电路。电流检测放大器电路包括电池电流发生器，参考电流发生器和读出放大器。电池电流发生器包括连接到字线和位线的存储单元，并产生施加到存储单元的存储单元电流和用于对位线充电的位线充电电流。参考电流发生器包括虚拟位线和参考单元，并且产生施加到参考单元的参考单元电流和用于对虚拟位线进行充电的虚拟位线充电电流。感测放大器包括连接到电池电流发生器的用于接收存储器单元电流和位线充电电流的第一输入端子和连接到参考电流发生器的用于接收参考电池电流和虚拟电路的第二输入端子位线充电电流。感测放大器感测并放大通过第一输入端施加的电流与通过第二输入端施加的电流之间的差。在关闭电池的情况下，电流检测放大器电路无论位线充电电流如何，都高速地感测数据，并且具有用于稳定操作的对称结构。

6. 发明授权

US07142021B2 Data inversion circuits having a bypass mode of operation and methods of operating the same 有权
标题翻译：具有旁路操作模式的数据反转电路及其操作方法
公开(公告)号：US07142021B2
公开(公告)日：2006-11-28
申请号：US10991076
申请日：2004-11-17
申请人： Min-sang Park
发明人： Min-sang Park
IPC分类号： H03K19/20
CPC分类号： H03K19/00346 , H03K19/00361
摘要： An integrated circuit device includes a data inversion circuit configured to support an inversion mode of operation. The inversion mode of operation inverts selected ones of a plurality of N-bit words received in consecutive sequence at inputs thereof. The data inversion circuit is further configured to support a bypass mode of operation. The bypass mode of operation disables inversion of a second one of the plurality of N-bit words when a delay between receipt of the second one of the plurality of N-bit words and receipt of an immediately preceding first one of the plurality of N-bit words is greater than a predetermined time interval. Related methods are also discussed.
摘要翻译：集成电路装置包括配置为支持反转操作模式的数据反转电路。反转操作模式反转在其输入处以连续顺序接收的多个N位字中选定的一个。数据反转电路还被配置为支持旁路操作模式。旁路操作模式在接收到多个N位字中的第二个N位字之间的延迟和接收多个N位字之中的前一个第一个之前的第一个N位字时，位字大于预定时间间隔。还讨论了相关方法。

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