专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06995453B2 High voltage integrated circuit including bipolar transistor within high voltage island area 有权
公开(公告)号：US06995453B2
公开(公告)日：2006-02-07
申请号：US10241818
申请日：2002-09-10
申请人： Jong-jib Kim , Chang-ki Jeon , Sung-lyong Kim , Young-suk Choi , Min-hwan Kim
发明人： Jong-jib Kim , Chang-ki Jeon , Sung-lyong Kim , Young-suk Choi , Min-hwan Kim
IPC分类号： H01L27/102 , H01L29/70
CPC分类号： H01L21/761 , H01L27/0623 , H01L29/7322
摘要： In a high voltage integrated circuit, a low voltage region is separated from a high voltage region by a junction termination. A bipolar transistor in the high voltage region is surrounded by an isolation region having a low doping concentration. The use of a low-doped isolation region increases the size of an active region without reduction of a breakdown voltage.

2. 发明授权

US06833585B2 High voltage lateral DMOS transistor having low on-resistance and high breakdown voltage 有权
标题翻译：具有低导通电阻和高击穿电压的高电压横向DMOS晶体管
公开(公告)号：US06833585B2
公开(公告)日：2004-12-21
申请号：US10120207
申请日：2002-04-10
申请人： Min-hwan Kim , Chang-ki Jeon , Young-suk Choi
发明人： Min-hwan Kim , Chang-ki Jeon , Young-suk Choi
IPC分类号： H01L2976
CPC分类号： H01L29/7816 , H01L29/0634 , H01L29/7835
摘要： A high voltage lateral Double diffused Metal Oxide Semiconductor (DMOS) transistor includes a plurality of well regions of a first conductivity type formed to be spaced out within a well region of a second conductivity type between a channel region of the first conductivity type and a drain region of the second conductivity type. Most current is carried through some portions of the well region of the second conductivity type in which the well regions of the first conductivity do not appear so that the current carrying performance of the device is improved. When a bias voltage is applied to the drain region, the well region of the second conductivity type is completely depleted at other portions where the well region of the second conductivity type and the well regions of the first conductivity type alternately appear so that the breakdown voltage of the device can be increased. In addition, since the well region of the second conductivity type can be easily depleted, not only the breakdown voltage can be increased, but also the impurity concentration of the well region of the second conductivity type can be increased. Accordingly, the on-resistance of the device can be decreased.
摘要翻译：高压横向双扩散金属氧化物半导体（DMOS）晶体管包括多个第一导电类型的阱区，其形成为在第一导电类型的沟道区域和漏极之间的第二导电类型的阱区域内间隔开第二导电类型的区域。大多数电流通过第二导电类型的阱区的一些部分被携带，其中第一导电性的阱区不出现，从而提高了器件的载流性能。当偏置电压施加到漏极区域时，第二导电类型的阱区域在第二导电类型的阱区域和第一导电类型的阱区域交替出现的其它部分完全耗尽，使得击穿电压的设备可以增加。此外，由于第二导电类型的阱区域容易耗尽，不仅可以提高击穿电压，而且能够提高第二导电型阱区的杂质浓度。因此，可以降低器件的导通电阻。

3. 发明授权

US06486512B2 Power semiconductor device having high breakdown voltage and method for fabricating the same 有权
标题翻译：具有高击穿电压的功率半导体器件及其制造方法
公开(公告)号：US06486512B2
公开(公告)日：2002-11-26
申请号：US09790815
申请日：2001-02-23
申请人： Chang-ki Jeon , Jong-jib Kim , Young-suk Choi , Chang-seong Choi , Min-whan Kim
发明人： Chang-ki Jeon , Jong-jib Kim , Young-suk Choi , Chang-seong Choi , Min-whan Kim
IPC分类号： H01L2976
CPC分类号： H01L29/0692 , H01L29/0696 , H01L29/7835
摘要： A power semiconductor device and a method for fabricating the same are provided. The power semiconductor device includes a source structure having a projected portion with a tip-shaped end portion on its center and formed so as to surround a predetermined region of right and left and upper portions of the projected portion. Two drain structures are formed in a predetermined region surrounded by the source structure. Extended drain structures are formed around the drain structures and the extended drain structures function as a channel with a field effect channel between sides of the projected portion of the source structure. Accordingly, since there are no drain structures on the tip of the projected portion of the source structure, although a radius of curvature of the tip of the projected portion is small, a decrease in a breakdown voltage of a device due to the small radius of curvature of the tip of the projected portion can be suppressed. As a result, a power semiconductor device having a small radius of curvature of the source structure and a high breakdown voltage can be provided.
摘要翻译：提供了功率半导体器件及其制造方法。功率半导体器件包括源结构，其具有在其中心具有尖端形状的端部的突出部分并且形成为围绕突出部分的左右上部的预定区域。在由源结构包围的预定区域中形成两个漏极结构。在漏极结构周围形成扩展的漏极结构，并且延伸的漏极结构用作具有源结构的突出部分的侧面之间的场效应沟道的沟道。因此，由于在源极结构的突出部分的尖端上没有漏极结构，尽管突出部分的尖端的曲率半径小，但是由于半径小的部件，器件的击穿电压降低可以抑制突出部分的尖端的弯曲。结果，可以提供具有较小的源结构曲率半径和高击穿电压的功率半导体器件。

4. 发明授权

US06888210B2 Lateral DMOS transistor having reduced surface field 有权
标题翻译：具有减小的表面场的横向DMOS晶体管
公开(公告)号：US06888210B2
公开(公告)日：2005-05-03
申请号：US10360518
申请日：2003-02-07
申请人： Chang-ki Jeon , Min-hwan Kim , Sung-lyong Kim
发明人： Chang-ki Jeon , Min-hwan Kim , Sung-lyong Kim
IPC分类号： H01L29/772 , H01L21/266 , H01L21/336 , H01L21/74 , H01L23/58 , H01L29/08 , H01L29/10 , H01L29/76 , H01L29/78 , H01L29/94 , H01L31/0328 , H01L31/062 , H01L31/113
CPC分类号： H01L29/7816 , H01L21/266 , H01L21/74 , H01L29/0847 , H01L29/0878 , H01L29/1083 , H01L29/1095 , H01L29/66674 , H01L29/7835
摘要： In accordance with the present invention, a metal oxide semiconductor (MOS) transistor has a substrate of a first conductivity type. A drift region of a second conductivity type is formed over the substrate. A body region of the first conductivity type is formed in the drift region. A source region of the second conductivity is formed in the body region. A gate extends over a surface portion of the body region and overlaps each of the source region and the body region such that the surface portion of the body region forms a channel region of the transistor. A drain region of the second conductivity type is formed in the drift region. The drain region is laterally spaced from the source region a first predetermined distance. A first buried layer of the first conductivity type extends into the substrate and the drift region. The first buried layer laterally extends between the source and drain regions.
摘要翻译：根据本发明，金属氧化物半导体（MOS）晶体管具有第一导电类型的衬底。在衬底上形成第二导电类型的漂移区。在漂移区域中形成第一导电类型的体区。在身体区域中形成第二导电性的源极区域。栅极延伸在主体区域的表面部分上并且与源区域和主体区域中的每一个重叠，使得主体区域的表面部分形成晶体管的沟道区域。在漂移区域中形成第二导电类型的漏极区域。漏极区域与源极区域在第一预定距离上横向间隔开。第一导电类型的第一掩埋层延伸到衬底和漂移区域中。第一掩埋层在源区和漏区之间横向延伸。

5. 发明授权

US08399923B2 High voltage semiconductor device including field shaping layer and method of fabricating the same 有权
标题翻译：包括场成形层的高电压半导体器件及其制造方法
公开(公告)号：US08399923B2
公开(公告)日：2013-03-19
申请号：US12495948
申请日：2009-07-01
申请人： Yong-cheol Choi , Chang-ki Jeon , Min-suk Kim
发明人： Yong-cheol Choi , Chang-ki Jeon , Min-suk Kim
IPC分类号： H01L29/66
CPC分类号： H01L29/66681 , H01L29/0634 , H01L29/0878 , H01L29/1083 , H01L29/1095 , H01L29/402 , H01L29/41758 , H01L29/42368 , H01L29/7816
摘要： Provided are a high voltage semiconductor device in which a field shaping layer is formed on the entire surface of a semiconductor substrate and a method of fabricating the same. Specifically, the high voltage semiconductor device includes a first conductivity-type semiconductor substrate. A second conductivity-type semiconductor layer is disposed on a surface of the semiconductor substrate, and a first conductivity-type body region is formed in semiconductor layer. A second conductivity-type source region is formed in the body region. A drain region is formed in the semiconductor layer and is separated from the body region. The field shaping layer is formed on the entire surface of the semiconductor layer facing the semiconductor layer.
摘要翻译：提供一种在半导体衬底的整个表面上形成场成形层的高电压半导体器件及其制造方法。具体地，高电压半导体器件包括第一导电型半导体衬底。在半导体衬底的表面上设置第二导电型半导体层，在半导体层中形成第一导电型体区。在体区域中形成第二导电型源极区域。在半导体层中形成漏区，与体区分离。在与半导体层相对的半导体层的整个表面上形成场成形层。

6. 发明授权

US07906828B2 High-voltage integrated circuit device including high-voltage resistant diode 有权
标题翻译：高压集成电路器件包括耐高压二极管
公开(公告)号：US07906828B2
公开(公告)日：2011-03-15
申请号：US12397426
申请日：2009-03-04
申请人： Sung-lyong Kim , Chang-ki Jeon
发明人： Sung-lyong Kim , Chang-ki Jeon
IPC分类号： H01L21/70
CPC分类号： H01L29/8611 , H01L27/0629 , H01L29/0634 , H01L29/0692 , H01L29/0878 , H01L29/1095 , H01L29/42368 , H01L29/7816 , H01L29/868 , H01L2924/0002 , H03K17/6877 , H03K2217/0036 , H01L2924/00
摘要： A high-voltage integrated circuit includes a low-voltage circuit region having a plurality of semiconductor devices, which operate with respect to a ground voltage, a high-voltage circuit region having a plurality of semiconductor devices, which operate with respect to a voltage that varies from the ground voltage to a high voltage, a junction termination and a first isolation region electrically isolating the low-voltage circuit region from the high-voltage circuit region, a high-voltage resistant diode formed between the low-voltage circuit region and the high-voltage circuit region, and a second isolation region surrounding the high-voltage resistant diode and electrically isolating the high-voltage resistant diode from the low-voltage circuit region and the high-voltage circuit region.
摘要翻译：高压集成电路包括：具有多个相对于接地电压工作的半导体器件的低电压电路区域，具有多个半导体器件的高电压电路区域，其相对于从接地电压到高压变化，接合端接和将低压电路区域与高压电路区域电隔离的第一隔离区域，形成在低压电路区域和低压电路区域之间的高耐压二极管高压电路区域和围绕高耐压二极管的第二隔离区域，并且将高耐压二极管与低压电路区域和高压电路区域电隔离。

7. 发明申请

US20090243696A1 HIGH VOLTAGE SEMICONDUCTOR DEVICE HAVING SHIFTERS AND METHOD OF FABRICATING THE SAME 有权
标题翻译：具有变形器的高电压半导体器件及其制造方法
公开(公告)号：US20090243696A1
公开(公告)日：2009-10-01
申请号：US12402528
申请日：2009-03-12
申请人： Chang-ki Jeon , Min-suk Kim , Yong-cheol Choi
发明人： Chang-ki Jeon , Min-suk Kim , Yong-cheol Choi
IPC分类号： H03L5/00 , H01L21/76
CPC分类号： H01L27/088 , H01L21/823481
摘要： Provided are a high-voltage semiconductor device including a junction termination which electrically isolates a low voltage unit from a high voltage unit, and a method of fabricating the same. The high voltage semiconductor device includes a high voltage unit, a low voltage unit surrounding the high voltage unit, and a junction termination formed between the high voltage unit and the low voltage unit and surrounding the high voltage unit to electrically isolate the high voltage unit from the low voltage unit. The junction termination includes at least one level shifter which level shifts signals from the low voltage unit and supplies the same to the high voltage unit, a first device isolation region surrounding the high voltage unit to electrically isolate the high voltage unit from the level shifter, and a resistor layer electrically connecting neighboring level shifters.
摘要翻译：提供一种包括将低电压单元与高电压单元电隔离的接合端子的高压半导体器件及其制造方法。高电压半导体器件包括高电压单元，围绕高电压单元的低电压单元，以及形成在高电压单元和低电压单元之间并且围绕高电压单元的连接端子，以将高压单元与低压单位。所述连接终端包括至少一个电平移位器，其将来自所述低电压单元的信号电平移位并将其提供给所述高压单元;围绕所述高压单元的第一器件隔离区，以将所述高压单元与所述电平移位器电隔离; 以及电连接相邻电平移位器的电阻层。

8. 发明授权

US07518209B2 Isolation of a high-voltage diode between a high-voltage region and a low-voltage region of an integrated circuit 有权
标题翻译：在集成电路的高电压区域和低电压区域之间隔离高压二极管
公开(公告)号：US07518209B2
公开(公告)日：2009-04-14
申请号：US11378210
申请日：2006-03-16
申请人： Sung-lyong Kim , Chang-ki Jeon
发明人： Sung-lyong Kim , Chang-ki Jeon
IPC分类号： H01L29/93 , H01L23/58
CPC分类号： H01L29/8611 , H01L27/0629 , H01L29/0634 , H01L29/0692 , H01L29/0878 , H01L29/1095 , H01L29/42368 , H01L29/7816 , H01L29/868 , H01L2924/0002 , H03K17/6877 , H03K2217/0036 , H01L2924/00
摘要： Provided is a high-voltage integrated circuit device including a high-voltage resistant diode. The device includes a low-voltage circuit region having a plurality of semiconductor devices, which operate with respect to a ground voltage, a high-voltage circuit region having a plurality of semiconductor devices, which operate with respect to a voltage that varies from the ground voltage to a high voltage, a junction termination and a first isolation region electrically isolating the low-voltage circuit region from the high-voltage circuit region, a high-voltage resistant diode formed between the low-voltage circuit region and the high-voltage circuit region, and a second isolation region surrounding the high-voltage resistant diode and electrically isolating the high-voltage resistant diode from the low-voltage circuit region and the high-voltage circuit region. Therefore, a leakage current of the high-voltage resistant diode can be prevented.
摘要翻译：提供一种包括耐高压二极管的高压集成电路装置。该器件包括具有多个相对于接地电压工作的多个半导体器件的低电压电路区域，具有多个半导体器件的高电压电路区域，其相对于从地面变化的电压工作电压到高电压，接合端接和将低压电路区域与高压电路区域电隔离的第一隔离区域，形成在低压电路区域和高压电路之间的高耐压二极管以及围绕所述耐高压二极管的第二隔离区域，并且将所述耐高压二极管与所述低压电路区域和所述高压电路区域电隔离。因此，可以防止高耐压二极管的漏电流。

9. 发明授权

US07309894B2 High voltage gate driver integrated circuit including high voltage junction capacitor and high voltage LDMOS transistor 有权
标题翻译：高压栅极驱动器集成电路包括高压结电容和高压LDMOS晶体管
公开(公告)号：US07309894B2
公开(公告)日：2007-12-18
申请号：US11114693
申请日：2005-04-26
申请人： Chang-ki Jeon , Sung-lyong Kim , Tae-hun Kwon
发明人： Chang-ki Jeon , Sung-lyong Kim , Tae-hun Kwon
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L29/7816 , H01L27/0629 , H01L29/0615 , H01L29/0696 , H01L29/0878 , H01L29/7823
摘要： There is provided a high voltage gate driver integrated circuit. The high voltage gate driver integrated circuit includes: a high voltage region; a junction termination region surrounding the high voltage region; a low voltage region surrounding the junction termination region; a level shift transistor disposed between the high voltage region and the low voltage region, at least some portions of the level shift transistor being overlapped with the junction termination region; and/or a high voltage junction capacitor disposed between the high voltage region and the low voltage region, at least some portions of the high voltage junction capacitor being overlapped with the junction termination region.
摘要翻译：提供了高压栅极驱动器集成电路。高压栅极驱动器集成电路包括：高电压区域; 围绕高电压区域的接合端接区域; 围绕所述连接端接区域的低电压区域; 设置在所述高电压区域和所述低电压区域之间的电平移位晶体管，所述电平移位晶体管的至少一些部分与所述连接终止区域重叠; 和/或设置在高电压区域和低电压区域之间的高压结电容器，高压结电容器的至少一些部分与接合端接区域重叠。

10. 发明申请

US20110014760A1 Method of Forming Lateral Trench Gate FET with Direct Source-Drain Current Path 有权
标题翻译：形成具有直接源极漏极电流路径的侧沟栅极FET的方法
公开(公告)号：US20110014760A1
公开(公告)日：2011-01-20
申请号：US12890947
申请日：2010-09-27
申请人： Chang-ki Jeon , Gary Dolny
发明人： Chang-ki Jeon , Gary Dolny
IPC分类号： H01L21/336
CPC分类号： H01L29/7825 , H01L29/0634 , H01L29/0696
摘要： A method of forming a field effect transistor (FET) includes: forming a drift region comprising a stack of alternating conductivity type silicon layers; forming a drain region of a first conductivity type extending into the stack of alternating conductivity type silicon layers; forming a trench gate extending into the stack of alternating conductivity type silicon layers, the trench gate having a non-active sidewall and an active sidewall being perpendicular to one another; and forming a body region of a second conductivity type adjacent to the active sidewall of the trench gate, wherein the trench gate and the drain region are formed such that the non-active sidewall of the trench gate faces the drain region.
摘要翻译：形成场效应晶体管（FET）的方法包括：形成包括交替导电型硅层叠层的漂移区; 形成延伸到交替导电型硅层堆叠中的第一导电类型的漏区; 形成延伸到交替导电型硅层的堆叠中的沟槽栅极，所述沟槽栅极具有非活性侧壁和主动侧壁彼此垂直; 以及形成与所述沟槽栅极的有源侧壁相邻的第二导电类型的主体区域，其中所述沟槽栅极和漏极区域形成为使得所述沟槽栅极的非有源侧壁面向所述漏极区域。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式