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1. 发明申请

US20060113534A1 Test structure of semiconductor device 有权
公开(公告)号：US20060113534A1
公开(公告)日：2006-06-01
申请号：US11243595
申请日：2005-10-05
申请人： Min-chul Sun , Ja-hum Ku , Brian Greene , Manfred Eller , Roman Knoefler , Zhijiong Luo
发明人： Min-chul Sun , Ja-hum Ku , Brian Greene , Manfred Eller , Roman Knoefler , Zhijiong Luo
IPC分类号： H01L23/58
CPC分类号： G01R31/2884 , H01L22/34
摘要： A test structure of a semiconductor device with improved test reliability is provided. The test structure includes first and second active regions which are electrically isolated from each other and on which silicided first and second junction regions are formed, respectively, a semiconductor substrate or a well which is formed on lower parts of the first and second junction regions and has a conductivity type different from the first and second junction regions, and first and second pads through which an electrical signal is applied to the first and second junction regions and detected, and which are formed on the same level as a lower part of a metal layer or on the same level as the semiconductor substrate.

2. 发明授权

US07501651B2 Test structure of semiconductor device 有权
标题翻译：半导体器件的测试结构
公开(公告)号：US07501651B2
公开(公告)日：2009-03-10
申请号：US11243595
申请日：2005-10-05
申请人： Min-chul Sun , Ja-hum Ku , Brian J. Greene , Manfred Eller , Roman Knoefler , Zhijiong Luo
发明人： Min-chul Sun , Ja-hum Ku , Brian J. Greene , Manfred Eller , Roman Knoefler , Zhijiong Luo
IPC分类号： H01L23/58
CPC分类号： G01R31/2884 , H01L22/34
摘要： A test structure of a semiconductor device with improved test reliability is provided. The test structure includes first and second active regions which are electrically isolated from each other and on which silicided first and second junction regions are formed, respectively, a semiconductor substrate or a well which is formed on lower parts of the first and second junction regions and has a conductivity type different from the first and second junction regions, and first and second pads through which an electrical signal is applied to the first and second junction regions and detected, and which are formed on the same level as a lower part of a metal layer or on the same level as the semiconductor substrate.
摘要翻译：提供了具有改善的测试可靠性的半导体器件的测试结构。测试结构包括彼此电隔离并且分别在其上形成有硅化的第一和第二结区的第一和第二有源区，形成在第一和第二结区的下部的半导体衬底或阱，以及具有不同于第一和第二接合区域的导电类型，以及第一和第二焊盘，电信号通过该第一和第二焊盘施加到第一和第二接合区域并被检测，并且形成在与金属的下部相同的高度上层或与半导体衬底相同的水平。

3. 发明申请

US20060163569A1 Test structure of semiconductor device 有权
标题翻译：半导体器件的测试结构
公开(公告)号：US20060163569A1
公开(公告)日：2006-07-27
申请号：US11218397
申请日：2005-09-02
申请人： Min-chul Sun , Ja-hum Ku , Brian Greene , Manfred Eller , Wee Tan , Sunfei Fang , Zhijiong Luo
发明人： Min-chul Sun , Ja-hum Ku , Brian Greene , Manfred Eller , Wee Tan , Sunfei Fang , Zhijiong Luo
IPC分类号： H01L23/58 , H01L29/10
CPC分类号： H01L22/34
摘要： A test structure of a semiconductor device is provided. The test structure includes a semiconductor substrate, a transistor which includes a gate electrode formed on first and second active regions defined within the semiconductor substrate, and first and second junction regions which are arranged at both sidewalls of the gate electrode to reside within the first and second active regions and are silicided, and first and second pads through which electrical signals are applied to the silicided first and second junction regions and detected and which are formed on the same level as the gate electrode or the semiconductor substrate.
摘要翻译：提供半导体器件的测试结构。测试结构包括半导体衬底，晶体管，其包括形成在限定在半导体衬底内的第一和第二有源区上的栅极电极以及布置在栅电极的两个侧壁处以位于第一和第二有源区内的第一和第二接合区域，第二有源区，并且是硅化的，以及第一和第二焊盘，电信号通过该第一和第二焊盘施加到硅化的第一和第二结区，并被检测并形成在与栅电极或半导体衬底相同的高度上。

4. 发明授权

US07317204B2 Test structure of semiconductor device 有权
标题翻译：半导体器件的测试结构
公开(公告)号：US07317204B2
公开(公告)日：2008-01-08
申请号：US11218397
申请日：2005-09-02
申请人： Min-chul Sun , Ja-hum Ku , Brian J. Greene , Manfred Eller , Wee Lang Tan , Sunfei Fang , Zhijiong Luo
发明人： Min-chul Sun , Ja-hum Ku , Brian J. Greene , Manfred Eller , Wee Lang Tan , Sunfei Fang , Zhijiong Luo
IPC分类号： H01L23/58
CPC分类号： H01L22/34
摘要： A test structure of a semiconductor device is provided. The test structure includes a semiconductor substrate, a transistor which includes a gate electrode formed on first and second active regions defined within the semiconductor substrate, and first and second junction regions which are arranged at both sidewalls of the gate electrode to reside within the first and second active regions and are silicided, and first and second pads through which electrical signals are applied to the silicided first and second junction regions and detected and which are formed on the same level as the gate electrode or the semiconductor substrate.
摘要翻译：提供半导体器件的测试结构。测试结构包括半导体衬底，晶体管，其包括形成在限定在半导体衬底内的第一和第二有源区上的栅极电极以及布置在栅电极的两个侧壁处以位于第一和第二有源区内的第一和第二接合区域，第二有源区，并且是硅化的，以及第一和第二焊盘，电信号通过该第一和第二焊盘施加到硅化的第一和第二结区，并被检测并形成在与栅电极或半导体衬底相同的高度上。

5. 发明授权

US06797559B2 Method of fabricating semiconductor device having metal conducting layer 有权
标题翻译：制造具有金属导电层的半导体器件的方法
公开(公告)号：US06797559B2
公开(公告)日：2004-09-28
申请号：US10283844
申请日：2002-10-30
申请人： Chang-won Lee , Si-young Choi , Seong-jun Heo , Sung-man Kim , Min-chul Sun , Ja-hum Ku , Sun-pil Youn
发明人： Chang-won Lee , Si-young Choi , Seong-jun Heo , Sung-man Kim , Min-chul Sun , Ja-hum Ku , Sun-pil Youn
IPC分类号： H01L218242
CPC分类号： H01L29/6656 , H01L21/28044 , H01L29/4941
摘要： A method of manufacturing a semiconductor device having a metal conducting layer is provided. A metal conducting layer pattern having the metal conducting layer is formed on a semiconductor substrate. A portion of the metal conducting layer is partially exposed on the semiconductor substrate. The semiconductor substrate having the metal conducting layer pattern is loaded into a reaction chamber. A first silicon source gas is flowed into the reaction chamber. A silicon oxide layer is formed on the semiconductor substrate having the metal conducting layer pattern by supplying a second silicon source gas and an oxygen source gas into the reaction chamber.
摘要翻译：提供一种制造具有金属导电层的半导体器件的方法。具有金属导电层的金属导电层图案形成在半导体衬底上。金属导电层的一部分部分露出在半导体衬底上。具有金属导电层图案的半导体衬底被加载到反应室中。第一硅源气体流入反应室。通过向反应室供给第二硅源气体和氧源气体，在具有金属导电层图案的半导体衬底上形成氧化硅层。

6. 发明授权

US09508727B2 Integrated circuit device and method of manufacturing the same 有权
标题翻译：集成电路装置及其制造方法
公开(公告)号：US09508727B2
公开(公告)日：2016-11-29
申请号：US14853442
申请日：2015-09-14
申请人： Hong-bae Park , Ja-hum Ku , Myeong-cheol Kim , Jin-wook Lee , Sung-kee Han
发明人： Hong-bae Park , Ja-hum Ku , Myeong-cheol Kim , Jin-wook Lee , Sung-kee Han
IPC分类号： H01L21/336 , H01L29/78 , H01L27/088 , H01L29/66 , H01L27/11 , H01L27/092 , H01L27/02
CPC分类号： H01L27/1104 , H01L21/02164 , H01L21/0217 , H01L21/823821 , H01L21/823828 , H01L21/823871 , H01L21/823878 , H01L23/528 , H01L27/0207 , H01L27/0924 , H01L29/0649 , H01L29/66545 , H01L29/6656 , H01L29/785
摘要： A method includes providing a plurality of active regions on a substrate, and at least a first device isolation layer between two of the plurality of active regions, wherein the plurality of active regions extend in a first direction; providing a gate layer extending in a second direction, the gate layer forming a plurality of gate lines including a first gate line and a second gate line extending in a straight line with respect to each other and having a space therebetween, each of the first gate line and second gate line crossing at least one of the active regions, providing an insulation layer covering the first device isolation layer and covering the active region around each of the first and second gate lines; and providing an inter-gate insulation region in the space between the first gate line and the second gate line.
摘要翻译：一种方法包括在衬底上提供多个有源区，以及在所述多个有源区中的两个之间的至少第一器件隔离层，其中所述多个有源区在第一方向上延伸; 提供沿第二方向延伸的栅极层，所述栅极层形成多条栅极线，所述栅极线包括相对于彼此以直线延伸的第一栅极线和第二栅极线，所述第二栅极线和第二栅极线之间具有间隔，所述第一栅极线和第二栅极线交叉有效区域中的至少一个，提供覆盖第一器件隔离层并围绕第一和第二栅极线周围的有源区域覆盖的绝缘层; 以及在所述第一栅极线和所述第二栅极线之间的空间中提供栅极间绝缘区域。

7. 发明授权

US07781276B2 Methods of forming CMOS integrated circuits that utilize insulating layers with high stress characteristics to improve NMOS and PMOS transistor carrier mobilities 有权
标题翻译：使用具有高应力特性的绝缘层的CMOS集成电路的方法来改善NMOS和PMOS晶体管载流子迁移率
公开(公告)号：US07781276B2
公开(公告)日：2010-08-24
申请号：US12353519
申请日：2009-01-14
申请人： Kyoung-woo Lee , Ja-hum Ku , Seung-man Choi
发明人： Kyoung-woo Lee , Ja-hum Ku , Seung-man Choi
IPC分类号： H01L21/337
CPC分类号： H01L21/823807 , H01L29/7843
摘要： A CMOS integrated circuit has NMOS and PMOS transistors therein and an insulating layer extending on the NMOS transistors. The insulating layer is provided to impart a relatively large tensile stress to the NMOS transistors. In particular, the insulating layer is formed to have a sufficiently high internal stress characteristic that imparts a tensile stress in a range from about 2 gigapascals (2 GPa) to about 4 gigapascals (4 GPa) in the channel regions of the NMOS transistors.
摘要翻译： CMOS集成电路在其中具有NMOS和PMOS晶体管，并且在NMOS晶体管上延伸绝缘层。提供绝缘层以向NMOS晶体管施加相对较大的拉伸应力。特别地，绝缘层被形成为具有足够高的内部应力特性，其在NMOS晶体管的沟道区域中赋予约2千兆帕（2GPa）至约4千兆帕（4GPa）的范围内的拉伸应力。

8. 发明申请

US20080242015A1 Methods of Forming CMOS Integrated Circuit Devices Having Stressed NMOS and PMOS Channel Regions Therein and Circuits Formed Thereby 有权
标题翻译：形成CMOS集成电路器件的方法，其中形成了NMOS和PMOS沟道区域，由此形成电路
公开(公告)号：US20080242015A1
公开(公告)日：2008-10-02
申请号：US11691691
申请日：2007-03-27
申请人： Kyoung-woo Lee , Ja-hum Ku , Jae-eon Park
发明人： Kyoung-woo Lee , Ja-hum Ku , Jae-eon Park
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/76816 , H01L21/823871 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming CMOS integrated circuit devices include forming at least first, second and third transistors in a semiconductor substrate and then covering the transistors with one or more electrically insulating layers that impart a net stress (tensile or compressive) to channel regions of the transistors. The covering step may include covering the first and second transistors with a first electrically insulating layer having a sufficiently high internal stress characteristic to impart a net tensile (or compressive) stress in a channel region of the first transistor and covering the second and third transistors with a second electrically insulating layer having a sufficiently high internal stress characteristic to impart a net compressive (or tensile) stress in a channel region of the third transistor. A step may then performed to selectively remove a first portion of the second electrically insulating layer extending opposite a gate electrode of the second transistor. In addition, a step may be performed to selectively remove a first portion of the first electrically insulating layer extending opposite a gate electrode of the first transistor and a second portion of the second electrically insulating layer extending opposite a gate electrode of the third transistor.
摘要翻译：形成CMOS集成电路器件的方法包括在半导体衬底中形成至少第一，第二和第三晶体管，然后用一个或多个赋予晶体管沟道区的净应力（拉伸或压缩）的电绝缘层覆盖晶体管。覆盖步骤可以包括用具有足够高的内应力特性的第一电绝缘层覆盖第一和第二晶体管，以在第一晶体管的沟道区域中施加净拉伸（或压缩）应力，并用第具有足够高的内应力特性的第二电绝缘层，以在第三晶体管的沟道区域中施加净压缩（或拉伸）应力。然后执行步骤以选择性地去除与第二晶体管的栅电极相对延伸的第二电绝缘层的第一部分。此外，可以执行步骤以选择性地去除与第一晶体管的栅极相对延伸的第一电绝缘层的第一部分和与第三晶体管的栅电极相对延伸的第二电绝缘层的第二部分。

9. 发明授权

US07615432B2 HDP/PECVD methods of fabricating stress nitride structures for field effect transistors 有权
标题翻译：制造场效应晶体管的应力氮化物结构的HDP / PECVD方法
公开(公告)号：US07615432B2
公开(公告)日：2009-11-10
申请号：US11264865
申请日：2005-11-02
申请人： Junjung Kim , Jae-eun Park , Ja-hum Ku , Daewon Yang
发明人： Junjung Kim , Jae-eun Park , Ja-hum Ku , Daewon Yang
IPC分类号： H01L21/8238 , H01L21/8234 , H01L21/336 , H01L21/3205 , H01L21/4763 , H01L21/469
CPC分类号： H01L21/823425 , H01L21/823412 , H01L21/823468 , H01L21/823807 , H01L21/823864 , H01L29/7843
摘要： A stress nitride structure is formed on an integrated circuit field effect transistor by high density plasma (HDP) depositing a first stress nitride layer on the integrated circuit field effect transistor and then plasma enhanced chemical vapor depositing (PECVD) a second stress nitride layer on the first stress nitride layer. The first stress nitride layer is non-conformal and the second stress nitride layer is conformal. Related structures also are described.
摘要翻译：通过在集成电路场效应晶体管上沉积第一应力氮化物层，然后在等离子体增强化学气相沉积（PECVD）上的第二应力氮化物层上，通过高密度等离子体（HDP）在集成电路场效应晶体管上形成应力氮化物结构第一应力氮化物层。第一应力氮化物层是不共形的，第二应力氮化物层是共形的。还描述了相关结构。

10. 发明申请

US20090124093A1 Methods of Forming CMOS Integrated Circuits that Utilize Insulating Layers with High Stress Characteristics to Improve NMOS and PMOS Transistor Carrier Mobilities 有权
标题翻译：使用具有高应力特性的绝缘层的CMOS集成电路的形成方法来改善NMOS和PMOS晶体管载体的迁移率
公开(公告)号：US20090124093A1
公开(公告)日：2009-05-14
申请号：US12353519
申请日：2009-01-14
申请人： Kyoung-woo Lee , Ja-hum Ku , Seung-man Choi
发明人： Kyoung-woo Lee , Ja-hum Ku , Seung-man Choi
IPC分类号： H01L21/469
CPC分类号： H01L21/823807 , H01L29/7843
摘要： A CMOS integrated circuit has NMOS and PMOS transistors therein and an insulating layer extending on the NMOS transistors. The insulating layer is provided to impart a relatively large tensile stress to the NMOS transistors. In particular, the insulating layer is formed to have a sufficiently high internal stress characteristic that imparts a tensile stress in a range from about 2 gigapascals (2 GPa) to about 4 gigapascals (4 GPa) in the channel regions of the NMOS transistors.
摘要翻译： CMOS集成电路在其中具有NMOS和PMOS晶体管，并且在NMOS晶体管上延伸绝缘层。提供绝缘层以向NMOS晶体管施加相对较大的拉伸应力。特别地，绝缘层被形成为具有足够高的内部应力特性，其在NMOS晶体管的沟道区域中赋予约2千兆帕（2GPa）至约4千兆帕（4GPa）的范围内的拉伸应力。

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