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1. 发明申请

US20090250752A1 Methods of fabricating semiconductor device having a metal gate pattern 有权
标题翻译：制造具有金属栅极图案的半导体器件的方法
公开(公告)号：US20090250752A1
公开(公告)日：2009-10-08
申请号：US12457323
申请日：2009-06-08
申请人： Ja-Hum Ku , Chang-Won Lee , Seong-Jun Heo , Sun-Pil Youn , Sung-Man Kim
发明人： Ja-Hum Ku , Chang-Won Lee , Seong-Jun Heo , Sun-Pil Youn , Sung-Man Kim
IPC分类号： H01L29/94 , H01L29/78
CPC分类号： H01L21/823437 , H01L21/28247 , H01L29/4941 , H01L29/6656
摘要： A method of fabricating a semiconductor device having a metal gate pattern is provided in which capping layers are used to control the relative oxidation rates of portions of the metal gate pattern during a oxidation process. The capping layer may be a multilayer structure and may be etched to form insulating spacers on the sidewalls of the metal gate pattern. The capping layer(s) allow the use of a selective oxidation process, which may be a wet oxidation process utilizing partial pressures of both H2O and H2 in an H2-rich atmosphere, to oxidize portions of the substrate and metal gate pattern while suppressing the oxidation of metal layers that may be included in the metal gate pattern. This allows etch damage to the silicon substrate and edges of the metal gate pattern to be reduced while substantially maintaining the original thickness of the gate insulating layer and the conductivity of the metal layer(s).
摘要翻译：提供一种制造具有金属栅极图案的半导体器件的方法，其中使用覆盖层来控制氧化过程中金属栅极图案的部分的相对氧化率。覆盖层可以是多层结构，并且可以被蚀刻以在金属栅极图案的侧壁上形成绝缘间隔物。封盖层允许使用选择性氧化工艺，其可以是在富H2气氛中使用H 2 O和H 2的分压的湿式氧化工艺，以氧化基板和金属栅极图案的部分，同时抑制可以包括在金属栅极图案中的金属层的氧化。这允许对硅衬底的蚀刻损伤和金属栅极图案的边缘减小，同时基本上保持栅极绝缘层的原始厚度和金属层的导电性。

2. 发明授权

US07465617B2 Method of fabricating a semiconductor device having a silicon oxide layer, a method of fabricating a semiconductor device having dual spacers, a method of forming a silicon oxide layer on a substrate, and a method of forming dual spacers on a conductive material layer 有权
标题翻译：制造具有氧化硅层的半导体器件的方法，制造具有双间隔物的半导体器件的方法，在衬底上形成氧化硅层的方法以及在导电材料层上形成双间隔物的方法
公开(公告)号：US07465617B2
公开(公告)日：2008-12-16
申请号：US11269599
申请日：2005-11-09
申请人： Ja-Hum Ku , Chang-Won Lee , Seong-Jun Heo , Min-Chul Sun , Sun-Pil Youn
发明人： Ja-Hum Ku , Chang-Won Lee , Seong-Jun Heo , Min-Chul Sun , Sun-Pil Youn
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L21/02164 , H01L21/02211 , H01L21/02271 , H01L21/02362 , H01L21/31612 , H01L27/115
摘要： A method of fabricating a semiconductor device that includes dual spacers is provided. A nitrogen atmosphere may be created and maintained in a reaction chamber by supplying a nitrogen source gas. A silicon source gas and an oxygen source gas may then be supplied to the reaction chamber to deposit a silicon oxide layer on a semiconductor substrate, which may include a conductive material layer. A silicon nitride layer may then be formed on the silicon oxide layer by performing a general CVD process. Next, the silicon nitride layer may be etched until the silicon oxide layer is exposed. Because of the difference in etching selectivity between silicon nitride and silicon oxide, portions of the silicon nitride layer may remain on sidewalls of the conductive material layer. As a result, dual spacers formed of a silicon oxide layer and a silicon nitride layer may be formed on the sidewalls.
摘要翻译：提供一种制造包括双间隔件的半导体器件的方法。可以通过供应氮源气体在反应室中产生和保持氮气氛。然后可以将硅源气体和氧源气体供应到反应室以在可包括导电材料层的半导体衬底上沉积氧化硅层。然后可以通过执行一般CVD工艺在氧化硅层上形成氮化硅层。接下来，可以蚀刻氮化硅层直到氧化硅层露出。由于氮化硅和氧化硅之间的蚀刻选择性的差异，氮化硅层的部分可能残留在导电材料层的侧壁上。结果，可以在侧壁上形成由氧化硅层和氮化硅层形成的双重间隔物。

3. 发明申请

US20060163677A1 Methods of forming a semiconductor device having a metal gate electrode and associated devices 审中-公开
公开(公告)号：US20060163677A1
公开(公告)日：2006-07-27
申请号：US11386644
申请日：2006-03-22
申请人： Seong-Jun Heo , Sun-Pil Youn , Sung-Man Kim , Si-Young Choi , Gil-Heyun Choi , Ja-Hum Ku , Chang-Won Lee , Jong-Myeong Lee , Kwon-Sun Ryu
发明人： Seong-Jun Heo , Sun-Pil Youn , Sung-Man Kim , Si-Young Choi , Gil-Heyun Choi , Ja-Hum Ku , Chang-Won Lee , Jong-Myeong Lee , Kwon-Sun Ryu
IPC分类号： H01L29/94
CPC分类号： H01L21/28061 , H01L21/28088 , H01L29/4941 , H01L29/4966 , H01L29/6659 , H01L29/7833
摘要： Methods of forming a semiconductor device having a metal gate electrode include sequentially forming a gate insulator, a gate polysilicon layer and a metal-gate layer on a semiconductor substrate. The metal-gate layer and the gate polysilicon layer are sequentially patterned to form a gate pattern comprising a stacked gate polysilicon pattern and a metal-gate pattern. An oxidation barrier layer is formed to cover at least a portion of a sidewall of the metal-gate pattern.

4. 发明申请

US20060057807A1 Method of fabricating a semiconductor device having a silicon oxide layer, a method of fabricating a semiconductor device having dual spacers, a method of forming a silicon oxide layer on a substrate, and a method of forming dual spacers on a conductive material layer 有权
公开(公告)号：US20060057807A1
公开(公告)日：2006-03-16
申请号：US11269599
申请日：2005-11-09
申请人： Ja-Hum Ku , Chang-Won Lee , Seong-Jun Heo , Min-Chul Sun , Sun-Pil Youn
发明人： Ja-Hum Ku , Chang-Won Lee , Seong-Jun Heo , Min-Chul Sun , Sun-Pil Youn
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L21/02164 , H01L21/02211 , H01L21/02271 , H01L21/02362 , H01L21/31612 , H01L27/115
摘要： A method of fabricating a semiconductor device that includes dual spacers is provided. A nitrogen atmosphere may be created and maintained in a reaction chamber by supplying a nitrogen source gas. A silicon source gas and an oxygen source gas may then be supplied to the reaction chamber to deposit a silicon oxide layer on a semiconductor substrate, which may include a conductive material layer. A silicon nitride layer may then be formed on the silicon oxide layer by performing a general CVD process. Next, the silicon nitride layer may be etched until the silicon oxide layer is exposed. Because of the difference in etching selectivity between silicon nitride and silicon oxide, portions of the silicon nitride layer may remain on sidewalls of the conductive material layer. As a result, dual spacers formed of a silicon oxide layer and a silicon nitride layer may be formed on the sidewalls.

5. 发明授权

US06764961B2 Method of forming a metal gate electrode 有权
标题翻译：形成金属栅电极的方法
公开(公告)号：US06764961B2
公开(公告)日：2004-07-20
申请号：US09992980
申请日：2001-11-06
申请人： Ja-Hum Ku , Mahn-Ho Cho , Chul-Joon Choi , Seong-Jun Heo , Jun-Kyu Cho
发明人： Ja-Hum Ku , Mahn-Ho Cho , Chul-Joon Choi , Seong-Jun Heo , Jun-Kyu Cho
IPC分类号： H01L2131
CPC分类号： H01L29/4941 , H01L21/28088 , H01L21/32105 , H01L21/823437
摘要： The present invention includes a method of forming a metal gate electrode on which whiskers are not formed after performing a selective oxidation process and a subsequent heating process. The metal gate electrode is formed by forming a metal gate electrode pattern which is comprised of a polysilicon layer and a metal layer, and performing a selective oxidation process. After the selective oxidation process, the metal gate electrode undergoes a subsequent heating treatment. The selective oxidation process is carried out in a nitrogen containing gas ambient, so that a metal oxide layer is minimally formed on the metal layer. As a result, it is prevented from causing whiskers on the metal layer.
摘要翻译：本发明包括在进行选择氧化处理和随后的加热处理之后形成不形成晶须的金属栅电极的方法。通过形成由多晶硅层和金属层构成的金属栅电极图案，进行选择氧化处理，形成金属栅电极。在选择氧化处理之后，金属栅电极进行随后的加热处理。选择性氧化工艺在含氮气体环境中进行，使得在金属层上最少形成金属氧化物层。结果，防止在金属层上产生晶须。

6. 发明授权

US07772643B2 Methods of fabricating semiconductor device having a metal gate pattern 有权
标题翻译：制造具有金属栅极图案的半导体器件的方法
公开(公告)号：US07772643B2
公开(公告)日：2010-08-10
申请号：US12457323
申请日：2009-06-08
申请人： Ja-Hum Ku , Chang-Won Lee , Seong-Jun Heo , Sun-Pil Youn , Sung-Man Kim
发明人： Ja-Hum Ku , Chang-Won Lee , Seong-Jun Heo , Sun-Pil Youn , Sung-Man Kim
IPC分类号： H01L29/94 , H01L29/78
CPC分类号： H01L21/823437 , H01L21/28247 , H01L29/4941 , H01L29/6656
摘要： A method of fabricating a semiconductor device having a metal gate pattern is provided in which capping layers are used to control the relative oxidation rates of portions of the metal gate pattern during a oxidation process. The capping layer may be a multilayer structure and may be etched to form insulating spacers on the sidewalls of the metal gate pattern. The capping layer(s) allow the use of a selective oxidation process, which may be a wet oxidation process utilizing partial pressures of both H2O and H2 in an H2-rich atmosphere, to oxidize portions of the substrate and metal gate pattern while suppressing the oxidation of metal layers that may be included in the metal gate pattern. This allows etch damage to the silicon substrate and edges of the metal gate pattern to be reduced while substantially maintaining the original thickness of the gate insulating layer and the conductivity of the metal layer(s).
摘要翻译：提供一种制造具有金属栅极图案的半导体器件的方法，其中使用覆盖层来控制氧化过程中金属栅极图案的部分的相对氧化率。覆盖层可以是多层结构，并且可以被蚀刻以在金属栅极图案的侧壁上形成绝缘间隔物。封盖层允许使用选择性氧化工艺，其可以是在富H2气氛中使用H 2 O和H 2的分压的湿式氧化工艺，以氧化基板和金属栅极图案的部分，同时抑制可以包括在金属栅极图案中的金属层的氧化。这允许对硅衬底的蚀刻损伤和金属栅极图案的边缘减小，同时基本上保持栅极绝缘层的原始厚度和金属层的导电性。

7. 发明授权

US07306996B2 Methods of fabricating a semiconductor device having a metal gate pattern 有权
标题翻译：制造具有金属栅极图案的半导体器件的方法
公开(公告)号：US07306996B2
公开(公告)日：2007-12-11
申请号：US11498197
申请日：2006-08-03
申请人： Ja-Hum Ku , Chang-Won Lee , Seong-Jun Heo , Sun-Pil Youn , Sung-Man Kim
发明人： Ja-Hum Ku , Chang-Won Lee , Seong-Jun Heo , Sun-Pil Youn , Sung-Man Kim
IPC分类号： H01L21/336 , H01L21/3205 , H01L21/4763 , H01L21/44
CPC分类号： H01L21/823437 , H01L21/28247 , H01L29/4941 , H01L29/6656
摘要： A method of fabricating a semiconductor device having a metal gate pattern is provided in which capping layers are used to control the relative oxidation rates of portions of the metal gate pattern during a oxidation process. The capping layer may be a multilayer structure and may be etched to form insulating spacers on the sidewalls of the metal gate pattern. The capping layer(s) allow the use of a selective oxidation process, which may be a wet oxidation process utilizing partial pressures of both H2O and H2 in an H2-rich atmosphere, to oxidize portions of the substrate and metal gate pattern while suppressing the oxidation of metal layers that may be included in the metal gate pattern. This allows etch damage to the silicon substrate and edges of the metal gate pattern to be reduced while substantially maintaining the original thickness of the gate insulating layer and the conductivity of the metal layer(s).
摘要翻译：提供一种制造具有金属栅极图案的半导体器件的方法，其中使用覆盖层来控制氧化过程中金属栅极图案的部分的相对氧化率。覆盖层可以是多层结构，并且可以被蚀刻以在金属栅极图案的侧壁上形成绝缘间隔物。封盖层允许使用选择性氧化工艺，其可以是使用H 2 H 2 O和H 2 H 2的分压的H氧化方法 2极化气氛，以便在抑制可能包含在金属栅极图案中的金属层的氧化的同时氧化基板和金属栅极图案的部分。这允许对硅衬底的蚀刻损伤和金属栅极图案的边缘减小，同时基本上保持栅极绝缘层的原始厚度和金属层的导电性。

8. 发明申请

US20060270204A1 Methods of fabricating a semiconductor device having a metal gate pattern 有权
标题翻译：制造具有金属栅极图案的半导体器件的方法
公开(公告)号：US20060270204A1
公开(公告)日：2006-11-30
申请号：US11498195
申请日：2006-08-03
申请人： Ja-Hum Ku , Chang-Won Lee , Seong-Jun Heo , Sun-Pil Youn , Sung-Man Kim
发明人： Ja-Hum Ku , Chang-Won Lee , Seong-Jun Heo , Sun-Pil Youn , Sung-Man Kim
IPC分类号： H01L21/4763 , H01L21/3205
CPC分类号： H01L21/823437 , H01L21/28247 , H01L29/4941 , H01L29/6656
摘要： A method of fabricating a semiconductor device having a metal gate pattern is provided in which capping layers are used to control the relative oxidation rates of portions of the metal gate pattern during a oxidation process. The capping layer may be a multilayer structure and may be etched to form insulating spacers on the sidewalls of the metal gate pattern. The capping layer(s) allow the use of a selective oxidation process, which may be a wet oxidation process utilizing partial pressures of both H2O and H2 in an H2-rich atmosphere, to oxidize portions of the substrate and metal gate pattern while suppressing the oxidation of metal layers that may be included in the metal gate pattern. This allows etch damage to the silicon substrate and edges of the metal gate pattern to be reduced while substantially maintaining the original thickness of the gate insulating layer and the conductivity of the metal layer(s).
摘要翻译：提供一种制造具有金属栅极图案的半导体器件的方法，其中使用覆盖层来控制氧化过程中金属栅极图案的部分的相对氧化率。覆盖层可以是多层结构，并且可以被蚀刻以在金属栅极图案的侧壁上形成绝缘间隔物。封盖层允许使用选择性氧化工艺，其可以是使用H 2 H 2 O和H 2 H 2的分压的H氧化方法 2极化气氛，以便在抑制可能包含在金属栅极图案中的金属层的氧化的同时氧化基板和金属栅极图案的部分。这允许对硅衬底的蚀刻损伤和金属栅极图案的边缘减小，同时基本上保持栅极绝缘层的原始厚度和金属层的导电性。

9. 发明申请

US20060270205A1 Methods of fabricating a semiconductor device having a metal gate pattern 有权
公开(公告)号：US20060270205A1
公开(公告)日：2006-11-30
申请号：US11498197
申请日：2006-08-03
申请人： Ja-Hum Ku , Chang-Won Lee , Seong-Jun Heo , Sun-Pil Youn , Sung-Man Kim
发明人： Ja-Hum Ku , Chang-Won Lee , Seong-Jun Heo , Sun-Pil Youn , Sung-Man Kim
IPC分类号： H01L21/4763 , H01L23/52
CPC分类号： H01L21/823437 , H01L21/28247 , H01L29/4941 , H01L29/6656
摘要： A method of fabricating a semiconductor device having a metal gate pattern is provided in which capping layers are used to control the relative oxidation rates of portions of the metal gate pattern during a oxidation process. The capping layer may be a multilayer structure and may be etched to form insulating spacers on the sidewalls of the metal gate pattern. The capping layer(s) allow the use of a selective oxidation process, which may be a wet oxidation process utilizing partial pressures of both H2O and H2 in an H2-rich atmosphere, to oxidize portions of the substrate and metal gate pattern while suppressing the oxidation of metal layers that may be included in the metal gate pattern. This allows etch damage to the silicon substrate and edges of the metal gate pattern to be reduced while substantially maintaining the original thickness of the gate insulating layer and the conductivity of the metal layer(s).

10. 发明授权

US07098123B2 Methods of forming a semiconductor device having a metal gate electrode and associated devices 有权
标题翻译：形成具有金属栅电极和相关器件的半导体器件的方法
公开(公告)号：US07098123B2
公开(公告)日：2006-08-29
申请号：US10780244
申请日：2004-02-17
申请人： Seong-Jun Heo , Sun-Pil Youn , Sung-Man Kim , Si-Young Choi , Gil-Heyun Choi , Ja-Hum Ku , Chang-Won Lee , Jong-Myeong Lee , Kwon-Sun Ryu
发明人： Seong-Jun Heo , Sun-Pil Youn , Sung-Man Kim , Si-Young Choi , Gil-Heyun Choi , Ja-Hum Ku , Chang-Won Lee , Jong-Myeong Lee , Kwon-Sun Ryu
IPC分类号： H01L21/28
CPC分类号： H01L21/28061 , H01L21/28088 , H01L29/4941 , H01L29/4966 , H01L29/6659 , H01L29/7833
摘要： Methods of forming a semiconductor device having a metal gate electrode include sequentially forming a gate insulator, a gate polysilicon layer and a metal-gate layer on a semiconductor substrate. The metal-gate layer and the gate polysilicon layer are sequentially patterned to form a gate pattern comprising a stacked gate polysilicon pattern and a metal-gate pattern. An oxidation barrier layer is formed to cover at least a portion of a sidewall of the metal-gate pattern.
摘要翻译：形成具有金属栅电极的半导体器件的方法包括在半导体衬底上顺序地形成栅极绝缘体，栅极多晶硅层和金属栅极层。金属栅极层和栅极多晶硅层被顺序地图案化以形成包括堆叠栅极多晶硅图案和金属栅极图案的栅极图案。形成氧化阻挡层以覆盖金属 - 栅极图案的侧壁的至少一部分。

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