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    • 1. 发明申请
    • FLIP-FLOP CIRCUIT, FREQUENCY DIVIDER AND FREQUENCY DIVIDING METHOD
    • FLIP-FLOP电路,频率分频器和频率分割方法
    • US20130187686A1
    • 2013-07-25
    • US13569568
    • 2012-08-08
    • Min-Shueh YUANChien-Hung CHENShao-Yu LI
    • Min-Shueh YUANChien-Hung CHENShao-Yu LI
    • H03B19/12H03K19/096
    • H03K3/0375
    • In response to a first level of the clock signal, an inverting output of a flip-flop circuit is connected, via a non-inverting input thereof, to a first intermediate node of the flip-flop circuit and a non-inverting output of the flip-flop circuit is connected, via an inverting input thereof, to a second intermediate node of the flip-flop circuit. In response to a second level of the clock signal, the first intermediate node is connected, via a third intermediate node of the flip-flop circuit, to the non-inverting output and the second intermediate node is connected, via a fourth intermediate node of the flip-flop circuit, to the inverting output. A first cross-coupled gates arrangement of the flip-flop circuit is coupled between the first and second intermediate nodes. A second cross-coupled gates arrangement of the flip-flop circuit is coupled between the third and fourth intermediate nodes.
    • 响应于第一级时钟信号,触发器电路的反相输出经由其非反相输入连接到触发器电路的第一中间节点,并且该反相输出端 触发器电路经由其反相输入连接到触发器电路的第二中间节点。 响应于时钟信号的第二电平,第一中间节点经由触发器电路的第三中间节点连接到非反相输出端,并且第二中间节点经由第四中间节点 触发器电路,到反相输出。 触发器电路的第一交叉耦合门装置耦合在第一和第二中间节点之间。 触发器电路的第二交叉耦合栅极布置耦合在第三和第四中间节点之间。