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1. 发明申请

US20080199975A1 METHODS OF FORMING A METAL OXIDE LAYER PATTERN HAVING A DECREASED LINE WIDTH OF A PORTION THEREOF AND METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME 审中-公开
标题翻译：形成具有其部分的下降线宽度的金属氧化物层图案的方法和使用其制造半导体器件的方法
公开(公告)号：US20080199975A1
公开(公告)日：2008-08-21
申请号：US12032018
申请日：2008-02-15
申请人： Min-Joon Park , Chang-Jin Kang , Dong-Hyun Kim
发明人： Min-Joon Park , Chang-Jin Kang , Dong-Hyun Kim
IPC分类号： H01L21/18 , H01L21/3065
CPC分类号： H01L27/11521 , H01L21/0206 , H01L21/31116 , H01L21/31122 , H01L21/32136 , H01L27/115 , H01L27/11502 , H01L27/11507 , H01L28/55 , H01L29/40117
摘要： Provided herein are methods of forming a metal oxide layer pattern on a substrate including providing a preliminary metal oxide layer on a substrate; etching the preliminary metal oxide layer to provide a preliminary metal oxide layer pattern, wherein the line width of the preliminary metal oxide layer pattern gradually increases in a vertically downward direction; and etching the preliminary metal oxide layer pattern to form a metal oxide layer pattern in a manner so as to decrease the line width of a lower portion of the preliminary metal oxide layer. The present invention also provides methods of manufacturing a semiconductor device including forming a metal oxide layer and a first conductive layer on a substrate; etching the metal oxide layer to provide a preliminary metal oxide layer pattern, wherein the line width of the preliminary metal oxide layer pattern gradually increase in a vertically downward direction; etching the first conductive layer to provide a first conductive layer pattern; and etching the preliminary metal oxide layer pattern to provide a metal oxide layer pattern in a manner so as to decrease the line width of a lower portion of the preliminary metal oxide layer pattern.
摘要翻译：本文提供了在衬底上形成金属氧化物层图案的方法，包括在衬底上提供初步金属氧化物层; 蚀刻初始金属氧化物层以提供初步金属氧化物层图案，其中预备金属氧化物层图案的线宽在垂直向下的方向上逐渐增加; 并且以使得预备金属氧化物层的下部的线宽减小的方式蚀刻初步金属氧化物层图案以形成金属氧化物层图案。本发明还提供了制造半导体器件的方法，包括在衬底上形成金属氧化物层和第一导电层; 蚀刻金属氧化物层以提供初步金属氧化物层图案，其中初始金属氧化物层图案的线宽在垂直向下的方向上逐渐增加; 蚀刻第一导电层以提供第一导电层图案; 并且蚀刻初步金属氧化物层图案以提供金属氧化物层图案，以便减小初步金属氧化物层图案的下部的线宽度。

2. 发明授权

US09093500B2 Methods of forming semiconductor device using bowing control layer 有权
标题翻译：使用弯曲控制层形成半导体器件的方法
公开(公告)号：US09093500B2
公开(公告)日：2015-07-28
申请号：US14247635
申请日：2014-04-08
申请人： Jae-Hong Park , Min-Joon Park , Jun-Ho Yoon , Gyung-Jin Min , Jin-Young Park , Je-Woo Han
发明人： Jae-Hong Park , Min-Joon Park , Jun-Ho Yoon , Gyung-Jin Min , Jin-Young Park , Je-Woo Han
IPC分类号： H01L21/311 , H01L21/768
CPC分类号： H01L21/76802 , H01L21/31144 , H01L21/76804 , H01L27/10852 , H01L28/90
摘要： A bowing control pattern is formed on an intermediate layer. A hardmask pattern is formed on the bowing control layer. The hardmask pattern has a first opening, and the bowing control pattern has a second opening. A third opening passes through the intermediate layer and is connected to the second opening. The bowing control pattern includes first and second edges on a lower end of the second opening, and a third edge on an upper end of the second opening. When a first point on the first edge, a second point on the second edge, and a third point on a horizontal line passing through the third edge are defined, an intersecting angle between a first side from the first point to the second point, and a second side from the second point to the third point is from about 50° to about 80°.
摘要翻译：在中间层上形成弯曲控制图案。在弓形控制层上形成硬掩模图案。硬掩模图案具有第一开口，并且弯曲控制图案具有第二开口。第三开口穿过中间层并连接到第二开口。弯曲控制图案包括在第二开口的下端上的第一边缘和第二边缘，以及在第二开口的上端上的第三边缘。当第一边缘上的第一点，第二边缘上的第二点和通过第三边缘的水平线上的第三点被限定时，从第一点到第二点的第一侧之间的相交角，以及从第二点到第三点的第二侧为约50°至约80°。

3. 发明授权

US09054054B2 Methods of forming patterns and methods of manufacturing semiconductor devices using the same 有权
标题翻译：形成图案的方法和使用其制造半导体器件的方法
公开(公告)号：US09054054B2
公开(公告)日：2015-06-09
申请号：US13164215
申请日：2011-06-20
申请人： Min-Joon Park , Seok-Hyun Lim
发明人： Min-Joon Park , Seok-Hyun Lim
IPC分类号： H01L21/311 , H01L21/3213 , H01L21/308 , H01L27/115 , H01L21/3205 , H01L21/4763
CPC分类号： H01L21/32139 , H01L21/3086 , H01L21/32136 , H01L21/32137 , H01L27/11541
摘要： In a method forming patterns, a layer on a substrate is patterned by a first etching process using an etch mask to form a plurality of first preliminary patterns and a plurality of second preliminary patterns. The second preliminary patterns are spaced apart from each other at a second distance larger than a first distance at which the first preliminary patterns are spaced apart. First and second coating layers are formed on sidewalls of the first and second preliminary patterns, respectively, and the first and second coating layers and portions of the first and second preliminary patterns are removed by a second etching process using the etch mask to form a plurality of first patterns and a plurality of second patterns. The first patterns have widths that are smaller than widths of the first preliminary patterns. The first patterns may have generally vertical sidewalls relative to the substrate.
摘要翻译：在形成图案的方法中，通过使用蚀刻掩模的第一蚀刻工艺对衬底上的层进行构图，以形成多个第一初步图案和多个第二预备图案。第二初步图案在第二距离处彼此间隔开，第二距离大于第一预备图案间隔开的第一距离。第一和第二涂层分别形成在第一和第二初步图案的侧壁上，并且通过使用蚀刻掩模的第二蚀刻工艺去除第一和第二涂层以及第一和第二初步图案的部分以形成多个的第一图案和多个第二图案。第一图案的宽度小于第一初步图案的宽度。第一图案可以具有相对于基底的大致垂直的侧壁。

4. 发明申请

US20150056805A1 METHODS OF FORMING SEMICONDUCTOR DEVICE USING BOWING CONTROL LAYER 有权
标题翻译：使用控制层形成半导体器件的方法
公开(公告)号：US20150056805A1
公开(公告)日：2015-02-26
申请号：US14247635
申请日：2014-04-08
申请人： Jae-Hong Park , Min-Joon Park , Jun-Ho Yoon , Gyung-Jin Min , Jin-Young Park , Je-Woo Han
发明人： Jae-Hong Park , Min-Joon Park , Jun-Ho Yoon , Gyung-Jin Min , Jin-Young Park , Je-Woo Han
IPC分类号： H01L21/768
CPC分类号： H01L21/76802 , H01L21/31144 , H01L21/76804 , H01L27/10852 , H01L28/90
摘要： A bowing control pattern is formed on an intermediate layer. A hardmask pattern is formed on the bowing control layer. The hardmask pattern has a first opening, and the bowing control pattern has a second opening. A third opening passes through the intermediate layer and is connected to the second opening. The bowing control pattern includes first and second edges on a lower end of the second opening, and a third edge on an upper end of the second opening. When a first point on the first edge, a second point on the second edge, and a third point on a horizontal line passing through the third edge are defined, an intersecting angle between a first side from the first point to the second point, and a second side from the second point to the third point is from about 50° to about 80°.
摘要翻译：在中间层上形成弯曲控制图案。在弓形控制层上形成硬掩模图案。硬掩模图案具有第一开口，并且弯曲控制图案具有第二开口。第三开口穿过中间层并连接到第二开口。弯曲控制图案包括在第二开口的下端上的第一边缘和第二边缘，以及在第二开口的上端上的第三边缘。当第一边缘上的第一点，第二边缘上的第二点和通过第三边缘的水平线上的第三点被限定时，从第一点到第二点的第一侧之间的相交角，以及从第二点到第三点的第二侧为约50°至约80°。

5. 发明授权

US08555810B2 Plasma dry etching apparatus having coupling ring with cooling and heating units 有权
标题翻译：等离子体干式蚀刻装置，其具有带有冷却和加热单元的耦合环
公开(公告)号：US08555810B2
公开(公告)日：2013-10-15
申请号：US12792915
申请日：2010-06-03
申请人： Min-Joon Park , Su-Hong Kim
发明人： Min-Joon Park , Su-Hong Kim
IPC分类号： H01L21/3065
CPC分类号： H01J37/32091 , H01J37/32724 , H01L21/31116 , H01L21/32137
摘要： A plasma dry etching apparatus includes a pedestal in a process chamber, the pedestal being configured to support a wafer, a cathode electrode and a plate electrode in the process chamber, the cathode and plate electrodes being configured to apply radio-frequency (RF) power, an edge ring on an edge of the pedestal, a coupling ring having a first side on the pedestal and a second side on the edge ring, an edge cooling unit in the coupling ring, the edge cooling unit being configured to cool the edge ring to drop a temperature of an extreme edge of the wafer, and an edge heating unit in the coupling ring, the edge heating unit being configured to heat the edge ring to raise the temperature of an extreme edge of the wafer.
摘要翻译：等离子体干蚀刻装置在处理室中包括基座，所述基座构造成在处理室中支撑晶片，阴极电极和平板电极，所述阴极和板电极被配置为施加射频（RF）功率，所述基座的边缘上的边缘环，在所述基座上具有第一侧的联接环和所述边缘环上的第二侧，所述联接环中的边缘冷却单元，所述边缘冷却单元被配置为冷却所述边缘环为了降低晶片的极端边缘的温度和耦合环中的边缘加热单元，边缘加热单元被配置为加热边缘环以升高晶片的最外边缘的温度。

6. 发明授权

US08236682B2 Method of forming contact structure 有权
标题翻译：形成接触结构的方法
公开(公告)号：US08236682B2
公开(公告)日：2012-08-07
申请号：US12750157
申请日：2010-03-30
申请人： Kyung-Rae Byun , Suk-Ho Joo , Min-Joon Park
发明人： Kyung-Rae Byun , Suk-Ho Joo , Min-Joon Park
IPC分类号： H01L21/4763
CPC分类号： H01L21/76879 , H01L21/76823 , H01L21/76843 , H01L21/76867 , H01L21/76876 , H01L2221/1094 , Y10S977/742 , Y10S977/936
摘要： Provided is a method of forming a contact structure. The method includes forming a conductive pattern on a substrate. An interlayer insulating layer covering the conductive pattern is formed. The interlayer insulating layer is patterned to form an opening partially exposing the conductive pattern. An oxide layer is formed on substantially the entire surface of the substrate on which the opening is formed. A reduction process is performed to reduce the oxide layer. Here, the oxide layer on a bottom region of the opening is reduced to a catalyst layer, and the oxide layer on a region other than the bottom region of the opening is reduced to a non-catalyst layer. A nano material is grown from the catalyst layer, so that a contact plug is formed in the opening.
摘要翻译：提供一种形成接触结构的方法。该方法包括在衬底上形成导电图案。形成覆盖导电图案的层间绝缘层。图案化层间绝缘层以形成部分地暴露导电图案的开口。在其上形成有开口的基板的整个表面上形成氧化物层。进行还原处理以减少氧化物层。这里，开口底部的氧化物层被还原为催化剂层，除开口底部以外的区域的氧化物层还原为非催化剂层。从催化剂层生长纳米材料，使得在开口中形成接触塞。

7. 发明申请

US20110312172A1 Methods of Forming Patterns and Methods of Manufacturing Semiconductor Devices Using the Same 有权
标题翻译：形成图案的方法和使用其制造半导体器件的方法
公开(公告)号：US20110312172A1
公开(公告)日：2011-12-22
申请号：US13164215
申请日：2011-06-20
申请人： Min-Joon Park , Seok-Hyun Lim
发明人： Min-Joon Park , Seok-Hyun Lim
IPC分类号： H01L21/3205 , H01L21/311
CPC分类号： H01L21/32139 , H01L21/3086 , H01L21/32136 , H01L21/32137 , H01L27/11541
摘要： In a method forming patterns, a layer on a substrate is patterned by a first etching process using an etch mask to form a plurality of first preliminary patterns and a plurality of second preliminary patterns. The second preliminary patterns are spaced apart from each other at a second distance larger than a first distance at which the first preliminary patterns are spaced apart. First and second coating layers are formed on sidewalls of the first and second preliminary patterns, respectively, and the first and second coating layers and portions of the first and second preliminary patterns are removed by a second etching process using the etch mask to form a plurality of first patterns and a plurality of second patterns. The first patterns have widths that are smaller than widths of the first preliminary patterns. The first patterns may have generally vertical sidewalls relative to the substrate.
摘要翻译：在形成图案的方法中，通过使用蚀刻掩模的第一蚀刻工艺对衬底上的层进行构图，以形成多个第一初步图案和多个第二预备图案。第二初步图案在第二距离处彼此间隔开，第二距离大于第一预备图案间隔开的第一距离。第一和第二涂层分别形成在第一和第二初步图案的侧壁上，并且通过使用蚀刻掩模的第二蚀刻工艺去除第一和第二涂层以及第一和第二初步图案的部分以形成多个的第一图案和多个第二图案。第一图案的宽度小于第一初步图案的宽度。第一图案可以具有相对于基底的大致垂直的侧壁。

8. 发明申请

US20100255674A1 METHOD OF FORMING CONTACT STRUCTURE 有权
标题翻译：形成接触结构的方法
公开(公告)号：US20100255674A1
公开(公告)日：2010-10-07
申请号：US12750157
申请日：2010-03-30
申请人： Kyung-Rae BYUN , Suk-Ho Joo , Min-Joon Park
发明人： Kyung-Rae BYUN , Suk-Ho Joo , Min-Joon Park
IPC分类号： H01L21/768
CPC分类号： H01L21/76879 , H01L21/76823 , H01L21/76843 , H01L21/76867 , H01L21/76876 , H01L2221/1094 , Y10S977/742 , Y10S977/936
摘要： Provided is a method of forming a contact structure. The method includes forming a conductive pattern on a substrate. An interlayer insulating layer covering the conductive pattern is formed. The interlayer insulating layer is patterned to form an opening partially exposing the conductive pattern. An oxide layer is formed on substantially the entire surface of the substrate on which the opening is formed. A reduction process is performed to reduce the oxide layer. Here, the oxide layer on a bottom region of the opening is reduced to a catalyst layer, and the oxide layer on a region other than the bottom region of the opening is reduced to a non-catalyst layer. A nano material is grown from the catalyst layer, so that a contact plug is formed in the opening.
摘要翻译：提供一种形成接触结构的方法。该方法包括在衬底上形成导电图案。形成覆盖导电图案的层间绝缘层。图案化层间绝缘层以形成部分地暴露导电图案的开口。在其上形成有开口的基板的整个表面上形成氧化物层。进行还原处理以减少氧化物层。这里，开口底部的氧化物层被还原为催化剂层，除开口底部以外的区域的氧化物层还原为非催化剂层。从催化剂层生长纳米材料，使得在开口中形成接触塞。

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