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1. 发明授权

US07405760B2 Image pickup device with non-molded DSP chip and manufacturing method 有权
标题翻译：具有非模制DSP芯片的图像拾取器件及其制造方法
公开(公告)号：US07405760B2
公开(公告)日：2008-07-29
申请号：US10347184
申请日：2003-01-21
申请人： Min Kyo Cho , Sa Yoon Kang , Young Hoon Ro , Young Shin Kwon
发明人： Min Kyo Cho , Sa Yoon Kang , Young Hoon Ro , Young Shin Kwon
IPC分类号： H04N5/225
CPC分类号： H04N5/2253 , H01L2224/32145 , H01L2224/48091 , H01L2224/92247 , H01L2924/00014
摘要： An image pickup device and a manufacturing method thereof. A digital signal processing (DSP) chip is attached on a first surface of a substrate. A CMOS image sensor (CIS) chip is attached on an active surface of the DSP chip. The DSP chip and the CIS chip may be electrically connected to the substrate by wire bonding. A housing kit having a lens configured to transmit an image to the DSP chip may be mounted on the substrate. An inner space between the housing kit and the substrate is not molded, thereby simplifying a manufacturing process and providing a thinner and/or lighter image pickup device.
摘要翻译：一种摄像装置及其制造方法。数字信号处理（DSP）芯片附着在基板的第一表面上。 CMOS图像传感器（CIS）芯片附着在DSP芯片的有源表面上。 DSP芯片和CIS芯片可以通过引线接合电连接到基板。具有被配置为将图像传送到DSP芯片的透镜的外壳套件可以安装在基板上。外壳套件和基板之间的内部空间不被模制，从而简化制造过程并提供更薄和/或更轻的图像拾取装置。

2. 发明授权

US06607938B2 Wafer level stack chip package and method for manufacturing same 有权
公开(公告)号：US06607938B2
公开(公告)日：2003-08-19
申请号：US10200077
申请日：2002-07-18
申请人： Yong Hwan Kwon , Sa Yoon Kang , Dong Hyeon Jang , Min Kyo Cho , Gu Sung Kim
发明人： Yong Hwan Kwon , Sa Yoon Kang , Dong Hyeon Jang , Min Kyo Cho , Gu Sung Kim
IPC分类号： H01L2144
CPC分类号： H01L21/568 , H01L21/6835 , H01L21/76898 , H01L23/3114 , H01L24/11 , H01L24/12 , H01L24/16 , H01L25/0657 , H01L25/50 , H01L2224/0231 , H01L2224/0401 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05647 , H01L2224/05655 , H01L2224/13099 , H01L2225/0652 , H01L2225/06524 , H01L2225/06541 , H01L2225/06572 , H01L2225/06582 , H01L2225/06586 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/181 , H01L2924/351 , H01L2924/00 , H01L2924/00014 , H01L2924/01028 , H01L2924/013
摘要： A wafer level chip package has a redistrubution substrate, at least one lower semiconductor chip stacked on the redisctribution substrate, and an uppermost semiconductor chip. The redistribution substrate has a redistribution layer and substrate pads connected to the redistribution layer. The lower semiconductor chip is stacked on the redistribution layer and may have through holes for partially exposing the redistribution layer, the through holes corresponding to the substrate pads, and having conductive filling material filling the through holes. The uppermost semiconductor chip may have the same elements as the lower semiconductor chip, and may be flip chip bonded to the through holes. The package may further have a filling layer for filling areas between chips, a metal lid for coating most of the external surfaces, and external connection terminals formed on and electrically connected to the exposed redistribution layer from the first dielectric layer of the redistribution substrate.

3. 发明授权

US07208343B2 Semiconductor chip, chip stack package and manufacturing method 有权
标题翻译：半导体芯片，芯片堆栈封装及制造方法
公开(公告)号：US07208343B2
公开(公告)日：2007-04-24
申请号：US11017805
申请日：2004-12-22
申请人： Young Hee Song , Sa Yoon Kang , Min Young Son
发明人： Young Hee Song , Sa Yoon Kang , Min Young Son
IPC分类号： H01L21/00
CPC分类号： H01L25/0657 , H01L24/24 , H01L24/82 , H01L2224/24145 , H01L2224/48091 , H01L2225/0651 , H01L2225/06551 , H01L2225/06589 , H01L2924/01078 , H01L2924/01079 , H01L2924/15311 , H01L2924/30107 , H01L2924/00014
摘要： A semiconductor chip with conductive wiring that is routed to the edge of the substrate from the chip's backside. A plurality of such semiconductor chips are stacked and electrically connected using a wiring element that is a circuit board or conductive adhesive strips. The wiring element connects the conductive wiring of each semiconductor chip along the sides of the chips to the package substrate. A method of manufacturing the semiconductor chip includes batch manufacturing a plurality of die on a wafer with an active surface on which a plurality bonding pads are formed, and a backside which is the rear side of the active surface; forming a circuit groove on the backside; applying conductive wiring on the circuit groove using a conductive material; and separating the wafer into a plurality of semiconductor chips. A method of manufacturing the chip stack package with a plurality of such semiconductor chips having bump pads and connection pads routed to the side surface of the semiconductor chip includes stacking and bonding the bonding pad of the upper semiconductor chip on the bump pad of a lower semiconductor chip; electrically connecting the bonding pad of the lowest semiconductor chip to the substrate by bump bonding electrically connecting the wiring element to the connection pad of the semiconductor chip and the substrate; and connecting an external connection to the substrate.
摘要翻译：具有导电布线的半导体芯片，其从芯片的背面引导到衬底的边缘。多个这样的半导体芯片被堆叠并使用作为电路板或导电粘合带的布线元件电连接。布线元件将每个半导体芯片的导体布线沿着芯片的侧面连接到封装基板。制造半导体芯片的方法包括在其上形成有多个焊盘的有源表面的晶片上分批制造多个管芯，以及作为有源表面的后侧的背面; 在背面形成电路槽; 使用导电材料在电路槽上施加导电布线; 并将晶片分离成多个半导体芯片。制造具有多个这样的具有凸块焊盘的半导体芯片的芯片堆叠封装的方法和布置到半导体芯片的侧表面的连接焊盘包括将上部半导体芯片的焊盘堆叠并粘合到下半导体的凸块焊盘上芯片; 通过将布线元件电连接到半导体芯片和衬底的连接焊盘的凸起接合将最低半导体芯片的焊盘电连接到衬底; 并将外部连接连接到基板。

4. 发明授权

US06376279B1 method for manufacturing a semiconductor package 有权
标题翻译：半导体封装的制造方法
公开(公告)号：US06376279B1
公开(公告)日：2002-04-23
申请号：US09482216
申请日：2000-01-12
申请人： Yong Hwan Kwon , Sa Yoon Kang , Nam Seog Kim , Dong Hyeon Jang
发明人： Yong Hwan Kwon , Sa Yoon Kang , Nam Seog Kim , Dong Hyeon Jang
IPC分类号： H01L2144
CPC分类号： H01L24/11 , H01L23/3114 , H01L23/49816 , H01L23/49827 , H01L24/02 , H01L24/12 , H01L24/16 , H01L24/97 , H01L2224/0231 , H01L2224/02333 , H01L2224/0401 , H01L2224/1134 , H01L2224/11822 , H01L2224/131 , H01L2224/16237 , H01L2224/9202 , H01L2224/92144 , H01L2224/97 , H01L2924/00013 , H01L2924/01006 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01046 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/12044 , H01L2924/14 , H01L2924/15184 , H01L2924/15311 , H01L2924/30105 , H01L2924/351 , H01L2924/00014 , H01L2224/13099 , H01L2924/00
摘要： A semiconductor package manufacturing method includes: providing a rerouting film; attaching a semiconductor wafer having integrated circuits to the rerouting film, such that chip pads of the integrated circuits correspond to via holes of the rerouting film; forming a solder filling in each of the via holes to electrically connect the chip pads to the metal pattern layer; forming external terminals on terminal pads of the rerouting film; and separating the wafer and the rerouting film into individual semiconductor packages. A method further includes forming a protection layer on the solder filling. Instead of the semiconductor wafer, individual integrated circuit chips can be attached on the rerouting film. The semiconductor package includes: an integrated circuit having chip pads; a substrate attached to the integrated circuit so that via holes of the substrate are above the chip pads; solder fillings inside the via holes, the solder fillings electrically connecting the chips pads to the pattern metal layer; and another dielectric layer between the substrate and the semiconductor integrated circuit. The semiconductor package further includes external terminals, interconnection bumps on the chip pads, and polymer protection layers on the solder fillings.
摘要翻译：半导体封装制造方法包括：提供重新布线膜; 将具有集成电路的半导体晶片连接到重新布线膜，使得集成电路的芯片焊盘对应于重新布线膜的通孔; 在每个所述通孔中形成焊料填充物，以将所述芯片焊盘电连接到所述金属图案层; 在重新布线膜的端子焊盘上形成外部端子; 以及将所述晶片和所述重新布线膜分离成单独的半导体封装。一种方法还包括在焊料填充物上形成保护层。代替半导体晶片，各个集成电路芯片可以附着在重新布线的薄膜上。半导体封装包括：具有芯片焊盘的集成电路; 附着到集成电路的衬底，使得衬底的通孔位于芯片焊盘之上; 通孔内的焊料填充物，焊料填充物将芯片焊盘电连接到图案金属层; 以及衬底和半导体集成电路之间的另一介质层。半导体封装还包括外部端子，芯片焊盘上的互连凸块和焊料填充物上的聚合物保护层。

5. 发明授权

US07115483B2 Stacked chip package having upper chip provided with trenches and method of manufacturing the same 有权
公开(公告)号：US07115483B2
公开(公告)日：2006-10-03
申请号：US10962591
申请日：2004-10-13
申请人： Yong Hwan Kwon , Se Yong Oh , Sa Yoon Kang
发明人： Yong Hwan Kwon , Se Yong Oh , Sa Yoon Kang
IPC分类号： H01L21/00 , H01L21/44 , H01L21/30 , H01L23/02
CPC分类号： H01L23/3121 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L29/0657 , H01L2224/05599 , H01L2224/32145 , H01L2224/32225 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/73265 , H01L2224/85399 , H01L2225/0651 , H01L2225/06555 , H01L2924/00014 , H01L2924/01068 , H01L2924/01078 , H01L2924/10158 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： A stacked chip package includes a substrate having an upper surface and a lower surface, a first semiconductor chip having an upper surface and a lower surface, wherein the lower surface of the first semiconductor chip is attached to the upper surface of the substrate and the upper surface of the first semiconductor chip includes a plurality of first electrode pads, and a second semiconductor chip having an upper surface and a lower surface. The lower surface of the second semiconductor chip is attached to the upper surface of the first semiconductor chip, and the lower surface of the second semiconductor chip includes trenches that correspond to the locations of the first electrode pads on the upper surface of the first semiconductor chip.

6. 发明授权

US06849802B2 Semiconductor chip, chip stack package and manufacturing method 有权
标题翻译：半导体芯片，芯片堆栈封装及制造方法
公开(公告)号：US06849802B2
公开(公告)日：2005-02-01
申请号：US10357376
申请日：2003-02-04
申请人： Young Hee Song , Sa Yoon Kang , Min Young Son
发明人： Young Hee Song , Sa Yoon Kang , Min Young Son
IPC分类号： H01L25/18 , H01L21/60 , H01L23/52 , H01L25/065 , H01L25/07 , H01L23/02
CPC分类号： H01L25/0657 , H01L24/24 , H01L24/82 , H01L2224/24145 , H01L2224/48091 , H01L2225/0651 , H01L2225/06551 , H01L2225/06589 , H01L2924/01078 , H01L2924/01079 , H01L2924/15311 , H01L2924/30107 , H01L2924/00014
摘要： A semiconductor chip has connection lines that are routed to the side surface from bump pads on the back surface of the chip. Such semiconductor chips are stacked on a circuit board to form a chip stack package while bumps are interposed between the bump pads of the lower chip and bonding pads of the upper chip. Further, an interconnecting member such as a conductive adhesive or a wiring board is applied to the side surfaces of the stacked chips such that the connection lines are connected to the interconnecting member. Therefore, the centrally disposed bonding pads of the chips are electrically connected to the circuit board through the bumps, the bump pad, the connection lines and the interconnecting member. The semiconductor chip may have heat dissipation part formed on the back surface. Methods of manufacturing the semiconductor chip and the chip stack package are also provided.
摘要翻译：半导体芯片具有从芯片背表面上的凸块焊接到侧表面的连接线。这样的半导体芯片堆叠在电路板上以形成芯片堆叠封装，同时将凸块插入下芯片的凸块焊盘和上芯片的焊盘之间。此外，将诸如导电粘合剂或布线板的互连构件施加到堆叠芯片的侧表面，使得连接线连接到互连构件。因此，芯片的集中设置的接合焊盘通过凸块，凸块焊盘，连接线和互连构件电连接到电路板。半导体芯片可以具有形成在背面上的散热部。还提供了制造半导体芯片和芯片堆叠封装的方法。

7. 发明授权

US06235552B1 Chip scale package and method for manufacturing the same using a redistribution substrate 有权
标题翻译：芯片尺寸封装及其制造方法
公开(公告)号：US06235552B1
公开(公告)日：2001-05-22
申请号：US09482160
申请日：2000-01-12
申请人： Yong Hwan Kwon , Sa Yoon Kang
发明人： Yong Hwan Kwon , Sa Yoon Kang
IPC分类号： H01L2144
CPC分类号： H01L24/94 , H01L23/3114 , H01L23/49816 , H01L23/49827 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/97 , H01L2221/68359 , H01L2224/0231 , H01L2224/02319 , H01L2224/0233 , H01L2224/02333 , H01L2224/03003 , H01L2224/03438 , H01L2224/0401 , H01L2224/13099 , H01L2224/16 , H01L2224/94 , H01L2224/97 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01046 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/15747 , H01L2924/30105 , H01L2924/351 , H01L2224/02 , H01L2924/00 , H01L2224/03
摘要： A method for manufacturing a chip scale package includes: providing a redistribution substrate; attaching a semiconductor wafer to the redistribution substrate; forming external terminals on the redistribution substrate; and separating the semiconductor wafer and the redistribution substrate into individual integrated circuits. The method can further include forming a buffer layer by filling a gap between the semiconductor wafer and the redistribution substrate with a dielectric material. Another method is the same as the method described above except that instead of the semiconductor wafer, individual integrated circuit chips attach to the redistribution substrate. Meanwhile, a semiconductor package includes: a semiconductor integrated circuit having chip pads formed thereon; interconnection bumps overlying on the chip pads; a patterned metal layer connecting to the interconnetion bumps; a first dielectric layer under the patterned metal layer; a second dielectric layer overlying on the patterned metal layer; and terminal pads connecting to the patterned metal layer. The semiconductor package can further include external terminals connecting to the terminal pads, a third dielectric layer filling a gap between the first dielectric layer and the semiconductor integrated circuit.
摘要翻译：芯片级封装的制造方法包括：提供再分布基板; 将半导体晶片附接到再分布基板; 在再分布基板上形成外部端子; 以及将半导体晶片和再分配基板分离成单独的集成电路。该方法还可以包括通过用介电材料填充半导体晶片和再分布基板之间的间隙来形成缓冲层。另一方法与上述方法相同，除了代替半导体晶片，各个集成电路芯片附着到再分布基板。同时，半导体封装包括：其上形成有芯片焊盘的半导体集成电路; 互连凸块覆盖在芯片焊盘上; 连接到互连凸块的图案化金属层; 图案化金属层下面的第一介电层; 覆盖在图案化金属层上的第二电介质层; 以及连接到图案化金属层的端子焊盘。半导体封装还可以包括连接到端子焊盘的外部端子，填充第一介电层和半导体集成电路之间的间隙的第三介电层。

8. 发明授权

US06903451B1 Chip scale packages manufactured at wafer level 有权
标题翻译：在晶圆级制造的芯片级封装
公开(公告)号：US06903451B1
公开(公告)日：2005-06-07
申请号：US09723953
申请日：2000-11-27
申请人： Nam Seog Kim , Dong Hyeon Jang , Sa Yoon Kang , Heung Kyu Kwon
发明人： Nam Seog Kim , Dong Hyeon Jang , Sa Yoon Kang , Heung Kyu Kwon
IPC分类号： H01L21/60 , H01L23/31 , H01L23/485 , H01L23/525 , H01L29/06 , H01L23/02
CPC分类号： H01L23/525 , H01L23/3114 , H01L24/11 , H01L24/12 , H01L24/94 , H01L29/0657 , H01L2224/0231 , H01L2224/0401 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05647 , H01L2224/10126 , H01L2224/13022 , H01L2224/13099 , H01L2224/274 , H01L2924/01013 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/014 , H01L2924/14 , H01L2924/00014 , H01L2924/013
摘要： In accordance with the present invention, a chip scale package (CSP) is manufactured at wafer-level. The CSP includes a chip, a conductor layer for redistribution of the chip pads of the chip, one or two insulation layers and multiple bumps, which are interconnected to respective chip pads by the conductor layer and are the terminals of the CSP. In addition, in order to improve the reliability of the CSP, a reinforcing layer, an edge protection layer and a chip protection layer are provided. The reinforcing layer absorbs stress applied to the bumps when the CSP is mounted on a circuit board and used for an extended period, and extends the life of the bumps, and thus, the life of the CSP. The edge protection layer and the chip protection layer prevent external force from damaging the CSP. After forming all elements constituting the CSP on the semiconductor wafer, the semiconductor wafer is sawed to produce individual CSPs.
摘要翻译：根据本发明，在晶片级制造芯片级封装（CSP）。 CSP包括芯片，用于芯片的芯片焊盘重新分配的导体层，一个或两个绝缘层和多个凸起，其通过导体层互连到相应的芯片焊盘，并且是CSP的端子。此外，为了提高CSP的可靠性，提供了增强层，边缘保护层和芯片保护层。当CSP安装在电路板上并且长时间使用时，加强层吸收施加到凸起的应力，并延长凸块的寿命，从而延长CSP的寿命。边缘保护层和芯片保护层防止外力损坏CSP。在半导体晶片上形成构成CSP的所有元件之后，锯切半导体晶片以产生单独的CSP。

9. 发明授权

US06818998B2 Stacked chip package having upper chip provided with trenches and method of manufacturing the same 失效
标题翻译：具有上部芯片的堆叠芯片封装提供沟槽及其制造方法
公开(公告)号：US06818998B2
公开(公告)日：2004-11-16
申请号：US10157272
申请日：2002-05-28
申请人： Yong Hwan Kwon , Se Yong Oh , Sa Yoon Kang
发明人： Yong Hwan Kwon , Se Yong Oh , Sa Yoon Kang
IPC分类号： H01L2334
CPC分类号： H01L23/3121 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L29/0657 , H01L2224/05599 , H01L2224/32145 , H01L2224/32225 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/73265 , H01L2224/85399 , H01L2225/0651 , H01L2225/06555 , H01L2924/00014 , H01L2924/01068 , H01L2924/01078 , H01L2924/10158 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： A stacked chip package includes a substrate having an upper surface and a lower surface, a first semiconductor chip having an upper surface and a lower surface, wherein the lower surface of the first semiconductor chip is attached to the upper surface of the substrate and the upper surface of the first semiconductor chip includes a plurality of first electrode pads, and a second semiconductor chip having an upper surface and a lower surface. The lower surface of the second semiconductor chip is attached to the upper surface of the first semiconductor chip, and the lower surface of the second semiconductor chip includes trenches that correspond to the locations of the first electrode pads on the upper surface of the first semiconductor chip.
摘要翻译：堆叠式芯片封装包括具有上表面和下表面的基板，具有上表面和下表面的第一半导体芯片，其中第一半导体芯片的下表面附着到基板的上表面，上表面第一半导体芯片的表面包括多个第一电极焊盘和具有上表面和下表面的第二半导体芯片。第二半导体芯片的下表面附接到第一半导体芯片的上表面，并且第二半导体芯片的下表面包括对应于第一半导体芯片的上表面上的第一电极焊盘的位置的沟槽。

10. 发明授权

US06791196B2 Semiconductor devices with bonding pads having intermetal dielectric layer of hybrid configuration and methods of fabricating the same 有权
标题翻译：具有接合焊盘的半导体器件具有混合配置的金属间电介质层及其制造方法
公开(公告)号：US06791196B2
公开(公告)日：2004-09-14
申请号：US10198001
申请日：2002-07-17
申请人： Dong Whee Kwon , Jin Hyuk Lee , Yun Heub Song , Sa Yoon Kang
发明人： Dong Whee Kwon , Jin Hyuk Lee , Yun Heub Song , Sa Yoon Kang
IPC分类号： H01L2348
CPC分类号： H01L24/13 , H01L24/03 , H01L24/05 , H01L24/11 , H01L2224/02166 , H01L2224/0401 , H01L2224/05073 , H01L2224/05093 , H01L2224/05096 , H01L2224/05552 , H01L2224/05556 , H01L2224/05624 , H01L2224/13099 , H01L2924/0001 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/00014
摘要： Devices that have bonding pads, and methods for fabricating the same. The bonding pads have two conductive layers, and an intermediate layer between them. The intermediate layer has a hybrid configuration of a relatively large conductive plate section, and a mixed plugs/mesh section. The plugs/mesh section has conductive portions interspersed with non-conducting portions, with features that are relatively small in size. The hybrid configuration achieves a proper balance between the plate section for the main electrical contact, and the plugs/mesh section for support and additional current density.
摘要翻译：具有接合焊盘的设备及其制造方法。接合焊盘具有两个导电层，以及它们之间的中间层。中间层具有相对较大的导电板部分和混合塞/网部分的混合构型。插头/网格部分具有散布有非导电部分的导电部分，具有尺寸相对较小的特征。混合配置在用于主电接触的板部分和用于支撑的插塞/网孔部分和附加电流密度之间实现了适当的平衡。

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