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1. 发明授权

US5186183A Method and apparatus for detecting micro-holes or examining the state of micro-holes formed on each of rod-like matters 失效
标题翻译：用于检测微孔或检查形成类似物质的微孔状态的方法和装置
公开(公告)号：US5186183A
公开(公告)日：1993-02-16
申请号：US623525
申请日：1990-12-07
申请人： Mikio Komori , Shuichi Sato , Kazuyu Adachi , Masayoshi Saito
发明人： Mikio Komori , Shuichi Sato , Kazuyu Adachi , Masayoshi Saito
IPC分类号： G01N15/08 , A24C5/34
CPC分类号： A24C5/3418 , Y10S131/904
摘要： In an apparatus for detecting micro-holes of a cigarette having a filtered section, cigarettes are successively carried to a support section which is rotated and each of the cigarettes is supported between pads 14a and 14b. The supported cigarette is moved to a pre-pressuring stage in which one end face of the cigarette is closed and a pre-pressure is applied to other end face of the cigarette from a pre-pressure source. Therefore, the cigarette is reached to a measuring stage in which a measuring pressure is applied to the other end face of the cigarette so that air flows through micro-holes of the filter section and a reduced pressure is appeared in the one end of the cigarette. The measuring and reduces pressures are detected by pressure transducers and electrical signals from the transducers are proceed so that dilution value of the cigarette is calculated.

2. 发明申请

US20080176150A1 Exposure mask and method of forming pattern 审中-公开
标题翻译：曝光掩模和形成图案的方法
公开(公告)号：US20080176150A1
公开(公告)日：2008-07-24
申请号：US12009309
申请日：2008-01-17
申请人： Masayoshi Saito
发明人： Masayoshi Saito
IPC分类号： G03F1/00 , G03F7/26
CPC分类号： G03F1/32 , G03F1/26
摘要： A method of forming a pattern according to the present invention comprising preparing a reduced projection exposure apparatus having a reduced projection ratio 1/m and a wavelength λ (nm) of exposing light and patterning a light shielding element pattern of a reticle mask on a resist film having a thickness tr (nm). The light shielding element pattern has a pattern opening portion having a minimum opening dimension D (nm). A thickness t0 of the light shielding element pattern is set so as to meet a relational equation of m*tr≦t0+5*D*D/λ. Preferably, the thickness t0 of the light shielding element pattern is set so as to meet a relational equation of m*tr≦t0+D*D/λ.
摘要翻译：根据本发明的形成图案的方法包括制备具有减小的投射比1 / m和曝光光的波长λ（nm）并且将掩模版掩模的遮光元件图案图案化在抗蚀剂上的减少投影曝光装置膜具有厚度tr（nm）。遮光元件图案具有具有最小开口尺寸D（nm）的图案开口部分。遮光元件图案的厚度t0被设定为满足m * tr <= t0 + 5 * D * D /λ的关系式。优选地，遮光元件图案的厚度t0设定为满足m * tr <= t0 + D * D /λ的关系式。

3. 发明授权

US06638811B2 Method of manufacturing a semiconductor integrated circuit device having a capacitor 有权
标题翻译：具有电容器的半导体集成电路器件的制造方法
公开(公告)号：US06638811B2
公开(公告)日：2003-10-28
申请号：US10157977
申请日：2002-05-31
申请人： Masayoshi Saito , Yoshitaka Nakamura , Hidekazu Goto , Keizo Kawakita , Satoru Yamada , Toshihiro Sekiguchi , Isamu Asano , Yoshitaka Tadaki , Takuya Fukuda , Masayuki Suzuki , Tsuyoshi Tamaru , Naoki Fukuda , Hideo Aoki , Masayoshi Hirasawa
发明人： Masayoshi Saito , Yoshitaka Nakamura , Hidekazu Goto , Keizo Kawakita , Satoru Yamada , Toshihiro Sekiguchi , Isamu Asano , Yoshitaka Tadaki , Takuya Fukuda , Masayuki Suzuki , Tsuyoshi Tamaru , Naoki Fukuda , Hideo Aoki , Masayoshi Hirasawa
IPC分类号： H01L218242
CPC分类号： H01L21/76855 , H01L21/28518 , H01L21/31604 , H01L21/76801 , H01L21/76828 , H01L21/76837 , H01L21/76843 , H01L21/76856 , H01L21/7687 , H01L27/10814 , H01L27/10885 , H01L27/10894 , H01L28/40
摘要： In a DRAM having a capacitor-over-bitline structure in which the capacitive insulating film of an information storing capacitive element C is formed of a high dielectric material such as Ta2O5 (tantalum oxide) film 46, the portions of bit lines BL and first-layer interconnect lines 23 to 26 of a peripheral circuit which are in contact with at least an underlying silicon oxide film 28 are formed of a W film, the bit lines BL and the interconnect lines 23 to 26 being arranged below the information storing capacitive element C, whereby the adhesion at the interface between the bit lines BL and the interconnect lines 23 to 26 and the silicon oxide film is improved in terms of high-temperature heat treatment to be performed when the capacitive insulating film is being formed.
摘要翻译：在具有电容器的位线结构的DRAM中，信息存储电容元件C的电容绝缘膜由诸如Ta 2 O 5（氧化钽）膜46的高电介质材料形成，位线BL和第一 - 与W膜形成的与外部电路至少底层的氧化硅膜28接触的层间布线23〜26，位线BL和布线23〜26配置在信息存储电容元件C的下方从而在形成电容绝缘膜时进行的高温热处理方面提高了位线BL与布线23〜26之间界面处的粘附性和氧化硅膜。

4. 发明授权

US06528403B2 Fabrication process of a semiconductor integrated circuit device 有权
公开(公告)号：US06528403B2
公开(公告)日：2003-03-04
申请号：US10013454
申请日：2001-12-13
申请人： Yoshikazu Tanabe , Isamu Asano , Makoto Yoshida , Naoki Yamamoto , Masayoshi Saito , Nobuyoshi Natsuaki
发明人： Yoshikazu Tanabe , Isamu Asano , Makoto Yoshida , Naoki Yamamoto , Masayoshi Saito , Nobuyoshi Natsuaki
IPC分类号： H01L214763
CPC分类号： H01L21/28247 , H01L21/28061 , H01L21/28176 , H01L21/32105 , H01L21/823437 , H01L21/823468 , H01L21/823828 , H01L21/823857 , H01L27/1052 , H01L27/10873 , H01L27/10894 , H01L29/4941
摘要： With a view to preventing the oxidation of a metal film at the time of light oxidation treatment after gate patterning and at the same time to making it possible to control the reproducibility of oxide film formation and homogeneity of oxide film thickness at gate side-wall end portions, in a gate processing step using a poly-metal, a gate electrode is formed by patterning a gate electrode material which has been deposited over a semiconductor wafer 1A having a gate oxide film formed thereon and has a poly-metal structure and then, the principal surface of the semiconductor wafer 1A heated to a predetermined temperature or vicinity thereof is supplied with a hydrogen gas which contains water at a low concentration, the water having been formed from hydrogen and oxygen by a catalytic action, to selectively oxidize the principal surface of the semiconductor wafer 1A, whereby the profile of the side-wall end portions of the gate electrode is improved.

5. 发明授权

US06432769B1 Semiconductor integrated circuit device and process for manufacture the same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US06432769B1
公开(公告)日：2002-08-13
申请号：US09642582
申请日：2000-08-22
申请人： Takuya Fukuda , Nobuyoshi Kobayashi , Yoshitaka Nakamura , Masayoshi Saito , Shinichi Fukada , Yoshifumi Kawamoto
发明人： Takuya Fukuda , Nobuyoshi Kobayashi , Yoshitaka Nakamura , Masayoshi Saito , Shinichi Fukada , Yoshifumi Kawamoto
IPC分类号： H01L2972
CPC分类号： H01L27/10808 , H01L27/108
摘要： The new structure of a memory cell which enables avoiding the problem of a step without increasing the number of processes, the structure of a semiconductor integrated circuit in which a common part of the same substrate in a manufacturing process is increased and the structure of the semiconductor integrated circuit which allows measures for environment obstacles without increasing the number of processes are disclosed. Memory cell structure in which a capacitor is formed in the uppermost layer of plural metal wiring layers by connecting the storage node of the capacitor to a diffusion layer via plugs and pads is adopted. It is desirable that a dielectric film formed in a metal wiring layer under the uppermost layer and a supplementary capacitor composed of a storage node and a plate electrode are connected to the capacitor. It is also desirable that the plate electrode of the capacitor covers the chip.
摘要翻译：存储单元的新结构能够在不增加处理次数的情况下避免步骤的问题，制造过程中同一基板的公共部分增加的半导体集成电路的结构和半导体的结构公开了不增加处理次数的环境障碍措施的集成电路。采用通过将电容器的存储节点经由插头和焊盘连接到扩散层，在多个金属布线层的最上层形成电容器的存储单元结构。最好将形成在最上层的金属布线层中的电介质膜和由存储节点和平板电极构成的辅助电容器连接到电容器。还希望电容器的平板电极覆盖芯片。

6. 发明授权

US06228791B1 Solid catalyst component and catalyst for olefin polymerization 失效
标题翻译：固体催化剂组分和烯烃聚合催化剂
公开(公告)号：US06228791B1
公开(公告)日：2001-05-08
申请号：US09331894
申请日：1999-07-06
申请人： Takuo Kataoka , Masayoshi Saito , Isa Nishiyama
发明人： Takuo Kataoka , Masayoshi Saito , Isa Nishiyama
IPC分类号： B01J2100
CPC分类号： C08F10/00 , C08F4/6567 , C08F4/6555 , C08F4/651 , C08F4/6465
摘要： The present invention is a solid catalyst component for polymerization of olefins prepared by contacting a magnesium compound, a tetravalent halogen-containing titanium compound, a diester of an aromatic dicarboxylic acid, an aromatic hydrocarbon and an organic aluminum compound containing a hydroxyl group represented by the following general formula (R1CO2)mAl(OH)3-m or aluminum hydroxide. The catalyst for polymerization of olefins comprising said solid catalyst component, an organic aluminum compound represented by the general formula R2pAlQ3-p and an organic silicon compound represented by the general formula R3qSi(OR4)4-q can retard the rate of forming a polymer having a low molecular weight or a low stereoregular polymer which is soluble in a polymerization solvent in slurry polymerization and can obtain a high stereoregular polymer in a high yield, and also can obtain a copolymer having an excellent property in a high yield in the copolymerization of olefins.
摘要翻译：本发明是通过使镁化合物，四价含卤素的钛化合物，芳族二羧酸的二酯，芳香族烃和含有羟基的有机铝化合物接触而制备的烯烃聚合用固体催化剂成分遵循通式（R1CO2）mA1（OH）3-m或氢氧化铝。包含所述固体催化剂组分，由通式R2pAlQ3-p表示的有机铝化合物和由通式R3qSi（OR4）4-q表示的有机硅化合物）的烯烃聚合催化剂可以延迟形成具有低分子量或低立构规整性聚合物，其在淤浆聚合中可溶于聚合溶剂，并且可以高产率获得高立构规整性聚合物，并且还可以获得在烯烃共聚合中具有优异性能的共聚物。

7. 发明授权

US4806335A Process for producing acicular iron .alpha.-oxyhydroxide particle powder 失效
标题翻译：生产针状铁α氧化氢颗粒粉的方法
公开(公告)号：US4806335A
公开(公告)日：1989-02-21
申请号：US119635
申请日：1987-11-12
申请人： Masayoshi Saito , Jiro I
发明人： Masayoshi Saito , Jiro I
IPC分类号： C01G49/02 , C01G49/06 , G11B5/706 , C01G45/02
CPC分类号： B82Y30/00 , C01G49/06 , G11B5/70663 , C01P2004/03 , C01P2004/10 , C01P2004/54 , C01P2004/62 , C01P2004/64
摘要： A process for producing acicular .alpha.-FeOOH particle powder having a narrow particle size distribution and a rectified shape and being highly dispersed is provided, which process comprises mixing with stirring an aqueous solution of a Fe(II) salt with an aqueous solution of an alkali in an equivalent ratio of alkali to Fe(II) salt of 1.5 or more, oxidizing the mixture with a O.sub.2 -containing gas, heat treating the resulting suspension of iron .alpha.-FeOOH particle powder to 60.degree. to 100.degree. C., further adding an aqueous solution of a FE(II) salt in a proportion of atom to molecule of Fe(II)/.alpha.-FeOOH of 0.5 to 10% and again oxidizing the mixture with a O.sub.2 -containing gas at 35.degree. to 55.degree. C.
摘要翻译：提供了具有窄的粒度分布和矫正形状并且高度分散的针状α-FeOOH颗粒粉末的方法，该方法包括将Fe（II）盐的水溶液与碱的水溶液碱金属与Fe（II）盐的当量比为1.5以上，用含O2气体氧化该混合物，将得到的铁α-FeOOH颗粒粉末悬浮液热处理至60℃至100℃，进一步加入 Fe（II）/α-FeOOH的原子与分子的比例为0.5至10％的FE（II）盐的水溶液，并再次在含有含氧气体的温度下在35至55℃下氧化该混合物。

8. 发明授权

US07968254B2 Photomask reticle for use in projection exposure, and manufacturing methods therefor 有权
标题翻译：用于投影曝光的光掩模掩模及其制造方法
公开(公告)号：US07968254B2
公开(公告)日：2011-06-28
申请号：US12078564
申请日：2008-04-01
申请人： Masayoshi Saito
发明人： Masayoshi Saito
IPC分类号： G03F1/00
CPC分类号： G03F1/32 , G03F1/36
摘要： A photomask reticle for use in projection exposure to form a resist pattern on a workable film formed over a semiconductor substrate, includes a first area in which a light shield is formed, a second area formed around said first area, a third area formed around said second area; and a fourth area formed around said third area, the areas being formed over a substrate, a relationship between transmissivities of said areas being second area transmissivity>fourth area transmissivity>third area transmissivity>first area transmissivity.
摘要翻译：一种用于投影曝光以形成在半导体衬底上形成的可加工膜上的抗蚀剂图案的光掩模掩模版包括形成有遮光罩的第一区域，围绕所述第一区域形成的第二区域，围绕所述第一区域形成的第三区域第二区以及围绕所述第三区域形成的第四区域，所述区域形成在衬底上，所述区域的透射率之间的关系是第二区域透射率>第四区域透射率>第三区域透射率>第一区域透射率。

9. 发明申请

US20080268381A1 Pattern forming method performing multiple exposure so that total amount of exposure exceeds threshold 审中-公开
标题翻译：图案形成方法进行多次曝光，使得总曝光量超过阈值
公开(公告)号：US20080268381A1
公开(公告)日：2008-10-30
申请号：US12081765
申请日：2008-04-21
申请人： Masayoshi Saito , Shinji Ohara
发明人： Masayoshi Saito , Shinji Ohara
IPC分类号： G03F7/20
CPC分类号： H01L21/0274 , G03F7/2022
摘要： A pattern forming method includes forming a resist film on a target film to be processed, which is formed on a substrate; and forming a basic pattern part in the resist film by multiple exposure using photomasks, wherein each exposure process is performed at an amount of exposure smaller than a threshold assigned to the resist film; and the resist film is developed after the total sum of the amounts of exposure through a plurality of exposure processes exceeds the threshold, so that the basic pattern part including a hole shape, which corresponds to each area where the total amount of exposure through the exposure processes via the photomasks exceeds the threshold, is formed in the resist film. The method also includes performing etching via the basic pattern part so as to form a desired pattern in the target film.
摘要翻译：图案形成方法包括在基板上形成的被处理对象膜上形成抗蚀剂膜; 并且使用光掩模通过多次曝光在抗蚀剂膜中形成基本图案部分，其中每个曝光处理以小于分配给抗蚀剂膜的阈值的曝光量进行; 并且在通过多次曝光处理的曝光量的总和超过阈值之后显影抗蚀剂膜，使得包括孔形状的基本图案部分对应于通过曝光的总曝光量的每个区域通过光掩模的处理超过阈值，形成在抗蚀剂膜中。该方法还包括通过基本图案部分进行蚀刻，以便在目标膜中形成所需的图案。

10. 发明授权

US06833331B2 Method of manufacturing semiconductor integrated circuit device having insulating film formed from liquid substance containing polymer of silicon, oxygen, and hydrogen 失效
标题翻译：具有由含有硅，氧和氢的聚合物的液体物质形成的绝缘膜的半导体集成电路器件的制造方法
公开(公告)号：US06833331B2
公开(公告)日：2004-12-21
申请号：US10303935
申请日：2002-11-26
申请人： Masayoshi Saito , Katsuhiko Hotta , Masayoshi Hirasawa , Masayuki Kojima , Hiroyuki Uchiyama , Hiroyuki Maruyama , Takuya Fukuda
发明人： Masayoshi Saito , Katsuhiko Hotta , Masayoshi Hirasawa , Masayuki Kojima , Hiroyuki Uchiyama , Hiroyuki Maruyama , Takuya Fukuda
IPC分类号： H01L2131
CPC分类号： H01L21/3124 , H01L21/02164 , H01L21/02216 , H01L21/02282 , H01L21/02337 , H01L21/3125 , H01L21/76802 , H01L21/76814 , H01L21/76816 , H01L21/76825 , H01L21/76826 , H01L21/76828 , H01L21/76831 , H01L27/10814 , H01L27/10894
摘要： An SOG film 16 obtained by heat-treating a polysilazan type SOG film at high temperature of about 800° C. is used as a planarized insulating film to be formed on the gate electrode (9; see FIGS. 31 and 32) of a MISFET (Qs, Qn, Qp) A polysilazan SOG film (57) not subjected to such a heat treatment is used as interlayer insulating film arranged among upper wiring layers (54, 55, 56, 62, 63).
摘要翻译：使用通过在约800℃的高温下热处理聚硅氮烷型SOG膜获得的SOG膜16作为形成在MISFET的栅极（9;参见图31和32）上的平坦化绝缘膜）（Qs，Qn，Qp）将不进行这种热处理的聚硅氮烷SOG膜（57）用作布置在上布线层（54,55,56,62,63）中的层间绝缘膜。

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