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1. 发明授权

US5187397A Integrated semiconductor circuit with improved boost operation speed 失效
标题翻译：集成式半导体电路，具有改进的升压运行速度
公开(公告)号：US5187397A
公开(公告)日：1993-02-16
申请号：US853296
申请日：1992-03-18
申请人： Miki Nishimori , Teruo Seki
发明人： Miki Nishimori , Teruo Seki
IPC分类号： G11C11/407 , G05F3/24 , G11C5/14 , G11C8/08 , G11C8/10 , G11C11/4074 , H03K19/094
CPC分类号： G05F3/24 , G11C11/4074 , G11C5/145 , G11C8/08 , G11C8/10
摘要： An integrated semiconductor circuit has a boost circuit that may improve boost operation speed. The boost circuit employs a P-channel type transistor as a driver. The back gate of the P-channel type transistor is connected to a charge-up circuit so that the back gate may be charged to a predetermined level before a boost signal is applied to the driver.

2. 发明授权

US5475639A Semiconductor memory device with improved speed for reading data 失效
标题翻译：半导体存储器件具有改善读取数据的速度
公开(公告)号：US5475639A
公开(公告)日：1995-12-12
申请号：US215023
申请日：1994-03-21
申请人： Akihiro Iwase , Teruo Seki , Shinji Nagai , Tadashi Ozawa
发明人： Akihiro Iwase , Teruo Seki , Shinji Nagai , Tadashi Ozawa
IPC分类号： G11C11/41 , G11C11/419 , G11C7/00
CPC分类号： G11C11/419
摘要： Disclosed is a semiconductor memory device which operates based on voltages from a high voltage power source and a low voltage power source. A plurality of memory cells are formed in a memory cell array. Plural pairs of bit lines are connected to the memory cells to transfer data signals read from the memory cells. A sense amplifier, which has a pair of input terminals, amplifies the data signal. A level shifter is selectively connected to plural pairs of bit lines to shift the level of the data signal of a selected pair of bit lines to a level near the operation point of the sense amplifier, and supplies a resultant data signal to the sense amplifier. The level shifter includes a first transistor for receiving the data signal, and a plurality of second transistors connected between the first transistor and the low voltage power source. The first transistor has a first terminal to be supplied with the data signal, a second terminal and a control electrode for receiving a control signal for transferring the data signal to the sense amplifier. The second transistors are connected between the second terminal of the first transistor and the low voltage power source. The output of the second terminal of the first transistor is input to the input terminals of the sense amplifier.
摘要翻译：公开了一种基于来自高压电源和低电压电源的电压进行工作的半导体存储器件。在存储单元阵列中形成多个存储单元。多对位线连接到存储器单元以传送从存储器单元读取的数据信号。具有一对输入端的读出放大器放大数据信号。电平移位器选择性地连接到多对位线，以将所选择的一对位线的数据信号的电平移动到读出放大器的操作点附近的电平，并将得到的数据信号提供给读出放大器。电平移位器包括用于接收数据信号的第一晶体管和连接在第一晶体管和低电压电源之间的多个第二晶体管。第一晶体管具有要提供数据信号的第一端子，第二端子和控制电极，用于接收用于将数据信号传送到读出放大器的控制信号。第二晶体管连接在第一晶体管的第二端子和低压电源之间。第一晶体管的第二端子的输出被输入到读出放大器的输入端。

3. 发明授权

US5719812A Semiconductor memory including bit line reset circuitry and a pulse generator having output delay time dependent on type of transition in an input signal 失效
标题翻译：半导体存储器包括位线复位电路和脉冲发生器，其具有取决于输入信号中的转换类型的输出延迟时间
公开(公告)号：US5719812A
公开(公告)日：1998-02-17
申请号：US718014
申请日：1996-09-03
申请人： Teruo Seki , Akihiro Iwase , Shinzi Nagai
发明人： Teruo Seki , Akihiro Iwase , Shinzi Nagai
IPC分类号： G11C7/12 , G11C7/22 , G11C11/413
CPC分类号： G11C7/12 , G11C7/22
摘要： A semiconductor memory includes a power down pulse generating circuit having an output delay time which is dependent on the type of change or transition in an input signal. The pulse generating circuit generates a power down signal at different times depending on whether the input signal changes from a first level to a second level or from the second level to the first level to prevent the power down signal from being output twice when an input clock signal has a pulse width shorter than a normal pulse width thereof. The power down pulse generating circuit generates the power down signal in response to a signal from address transition detection circuitry, and causes data read/write circuitry and bit line pulse generating circuitry to become inactive to reduce power consumption. The bit line pulse generating circuitry generates reset signals which may be used to reset or precharge the bit lines at different timings to reduce peak current in the semiconductor memory.
摘要翻译：半导体存储器包括具有取决于输入信号中的变化或转换的类型的输出延迟时间的掉电脉冲发生电路。脉冲发生电路根据输入信号是从第一电平变为第二电平还是从第二电平变为第一电平，在不同的时间产生掉电信号，以防止掉电信号在输入时钟信号具有比其正常脉冲宽度短的脉冲宽度。掉电脉冲产生电路响应于来自地址转换检测电路的信号产生掉电信号，并且使数据读/写电路和位线脉冲发生电路变为不活动以降低功耗。位线脉冲发生电路产生可用于在不同定时复位或预充电位线的复位信号，以减少半导体存储器中的峰值电流。

4. 发明授权

US4603404A Semiconductor memory device with redundant cells 失效
标题翻译：具有冗余单元的半导体存储器件
公开(公告)号：US4603404A
公开(公告)日：1986-07-29
申请号：US453575
申请日：1982-12-27
申请人： Takahiko Yamauchi , Teruo Seki , Keizo Aoyama
发明人： Takahiko Yamauchi , Teruo Seki , Keizo Aoyama
IPC分类号： G11C17/00 , G11C29/00 , G11C29/04 , G11C7/00
CPC分类号： G11C29/846
摘要： A semiconductor memory device in which the memory cells are arranged in matrix form and in which, when a defective cell exists among the memory cells and a row or column containing the defective cell is selected, the selected row or column is switched to a predetermined redundant row or a predetermined redundant column additionally and independently provided. A plurality of switching circuits are provided, each of the switching circuits being connected to the output of the decoder circuit, which select the row or the column of memory cells. A fusing circuit is connected to each of the switching circuits, and when the fuse in the fusing circuit is disconnected, the row or the column containing the defective cell is switched to the redundant row or the redundant column.
摘要翻译：一种半导体存储器件，其中存储器单元以矩阵形式布置，并且当存储器单元中存在缺陷单元并且选择了包含缺陷单元的行或列时，将所选择的行或列切换到预定的冗余行或预定的冗余列。提供多个开关电路，每个开关电路连接到选择存储单元的行或列的解码器电路的输出。熔断电路连接到每个开关电路，并且当熔断电路中的熔丝断开时，包含有缺陷单元的列或列被切换到冗余行或冗余列。

5. 发明授权

US4507574A Constant operation speed logic circuit 失效
标题翻译：恒定运行速度逻辑电路
公开(公告)号：US4507574A
公开(公告)日：1985-03-26
申请号：US449767
申请日：1982-12-14
申请人： Teruo Seki , Takahiko Yamauchi , Keizo Aoyama
发明人： Teruo Seki , Takahiko Yamauchi , Keizo Aoyama
IPC分类号： H03K19/0948 , G11C8/08 , G11C8/10 , G11C8/18 , G11C11/418 , H03K19/017 , H03K19/0944 , H03K19/094 , H03K19/096
CPC分类号： H03K19/09443 , G11C11/418 , G11C8/08 , G11C8/10 , G11C8/18 , H03K19/017
摘要： A logic circuit includes a plurality of input terminals (IN.sub.1, IN.sub.2, . . . ), an output terminal (OUT), a load (L), and at least two driver circuits (D.sub.1, D.sub.2, . . . ). Each of the driver circuits includes a plurality of gates connected in series, each gate being driven by one of the potentials at the input terminals. In addition, the first gates (Q.sub.11, Q.sub.22, . . . or Q.sub.11 ', Q.sub.22 ', . . . ) of the driver circuit connected directly to the output terminal are driven by different potentials at the input terminals.
摘要翻译：逻辑电路包括多个输入端子（IN1，IN2 ...），输出端子（OUT），负载（L）和至少两个驱动器电路（D1，D2 ...）。每个驱动器电路包括串联连接的多个栅极，每个栅极由输入端子中的一个电位驱动。此外，直接连接到输出端子的驱动电路的第一个门（Q11，Q22，...或Q11'，Q22'，...）由输入端的不同电位驱动。

6. 发明授权

US5281873A Sense amplifier control circuit 失效
标题翻译：感应放大器控制电路
公开(公告)号：US5281873A
公开(公告)日：1994-01-25
申请号：US62167
申请日：1993-05-17
申请人： Teruo Seki
发明人： Teruo Seki
IPC分类号： G05F3/20 , G11C7/06 , H03K5/24 , H03K19/00 , H03K17/60 , H03F3/45
CPC分类号： H03K19/0016 , G05F3/20 , G11C7/062 , H03K5/2436
摘要： A sense amplifier control circuit controls the activation and deactivation of sense amplifiers without a lowering of the operation speed of the sense amplifiers, correctly carries out a control operation without malfunctions, and is suitable for highly integrated circuits. The control circuit comprises a control unit, and each of the sense amplifiers comprises a pair of transistors forming a differential pair and a constant current source transistor connected to a common node of the differential pair. The control unit is connected to the constant current source transistors and generates a constant current source control signal in response to control signal indicating an activation or deactivation of the differential amplification operation of each differential pair.
摘要翻译：读出放大器控制电路控制读出放大器的激活和去激活，而不会降低读出放大器的工作速度，正确地执行无故障的控制操作，适用于高度集成的电路。控制电路包括控制单元，并且每个读出放大器包括形成差分对的一对晶体管和连接到差分对的公共节点的恒流源晶体管。控制单元连接到恒流源晶体管，并且响应于指示每个差分对的差分放大操作的激活或去激活的控制信号而产生恒定电流源控制信号。

7. 发明授权

US5064276A Light source for planar illumination in liquid crystal device 失效
标题翻译：液晶装置平面照明光源
公开(公告)号：US5064276A
公开(公告)日：1991-11-12
申请号：US374148
申请日：1989-06-30
申请人： Syuusuke Endo , Naofumi Aoyama , Toshihiko Yabuuchi , Teruo Seki
发明人： Syuusuke Endo , Naofumi Aoyama , Toshihiko Yabuuchi , Teruo Seki
IPC分类号： G02F1/1335 , F21V7/00 , F21V8/00 , G02B6/00 , G02F1/13357
CPC分类号： F21V7/00 , G02B6/0046 , G02B6/005 , G02B6/0068 , G02B6/0083
摘要： A light source device disposing light sources at both end faces of the transparent plate in which a surface of the transparent plate in the side of an observer (front surface) is formed as the inclined and curved surface in view of limiting reduction in quantity of light per unit area at the observing area being far from the light source within a certain level, the one surface of the transparent plate is formed as the rough surface to diffuse the incident light, the other surface of the transparent plate is formed as a mirror-surface, and a reflecting layer having a high lightness is disposed at the lower side of the transparent plate in order to provide sufficient luminance for observers.
摘要翻译：一种光源装置，在透明板的两个端面处设置光源，其中观察者侧（透明板的表面）的表面形成为倾斜和弯曲的表面，以限制光的减少在观察区域的远离光源的单位面积在一定水平内，透明板的一个表面形成为粗糙表面以扩散入射光，透明板的另一个表面形成为镜面 - 表面和具有高亮度的反射层设置在透明板的下侧，以便为观察者提供足够的亮度。

8. 发明授权

US4587639A Static semiconductor memory device incorporating redundancy memory cells 失效
标题翻译：结合冗余存储单元的静态半导体存储器件
公开(公告)号：US4587639A
公开(公告)日：1986-05-06
申请号：US593771
申请日：1984-03-27
申请人： Keizo Aoyama , Teruo Seki , Takahiko Yamauchi
发明人： Keizo Aoyama , Teruo Seki , Takahiko Yamauchi
IPC分类号： G11C7/12 , G11C8/18 , G11C11/419 , G11C29/00 , G11C7/00
CPC分类号： G11C29/83 , G11C11/419 , G11C29/832 , G11C7/12 , G11C8/18
摘要： In a static semiconductor memory device incorporating redundancy memory cells (C.sub.R0, C.sub.R1, . . . ), a connecting/disconnecting circuit is linked between a power supply terminal (V.sub.CC) and one of bit lines (B.sub.0, B.sub.0, . . . ), thereby reducing or cutting off a current flowing through a defective memory cell.
摘要翻译：在包含冗余存储单元（CR0，CR1 ...）的静态半导体存储器件中，连接/断开电路连接在电源端（VCC）和位线（B0，＆amp; B和...之一）之间，从而减少或切断流经缺陷存储单元的电流。

9. 发明授权

US4549199A Semiconductor device providing a contact structure which can be miniaturized 失效
标题翻译：提供可以小型化的接触结构的半导体器件
公开(公告)号：US4549199A
公开(公告)日：1985-10-22
申请号：US513611
申请日：1983-07-14
申请人： Takahiko Yamauchi , Teruo Seki , Keizo Aoyama
发明人： Takahiko Yamauchi , Teruo Seki , Keizo Aoyama
IPC分类号： H01L23/522 , H01L21/768 , H01L23/485 , H01L23/48 , H01L29/04 , H01L29/06
CPC分类号： H01L23/485 , H01L21/76895 , H01L2924/0002 , H01L2924/3011
摘要： A semiconductor device comprises a connection structure composed of a first conductive layer formed in or on a semiconductor substrate, a second conductive layer arranged adjacent to the first conductive layer, and a third conductive layer connecting the first conductive layer to the second conductive layer. The device of the present invention provides a contact structure which can be miniaturized.
摘要翻译：半导体器件包括由半导体衬底中或其上形成的第一导电层，与第一导电层相邻布置的第二导电层和将第一导电层连接到第二导电层的第三导电层构成的连接结构。本发明的装置提供可以小型化的接触结构。

10. 发明授权

US5747837A Semiconductor device having input protective function 失效
标题翻译：具有输入保护功能的半导体器件
公开(公告)号：US5747837A
公开(公告)日：1998-05-05
申请号：US763262
申请日：1996-12-10
申请人： Akihiro Iwase , Tomio Nakano , Teruo Seki
发明人： Akihiro Iwase , Tomio Nakano , Teruo Seki
IPC分类号： H01L21/8238 , H01L27/02 , H01L27/092 , H01L27/06
CPC分类号： H01L27/0259
摘要： A semiconductor device with an expanded range of a recommended condition for an input voltage is disclosed. In embodiment, the semiconductor device having input protection on an input terminal thereto, includes: a semiconductor region having a first conducting type, first and second diffusion regions defined in the semiconductor region and respectively having a second conducting type, and a transistor formed by using the semiconductor region as a base, the first diffusion region as a collector, and the second diffusion region as an emitter. The first diffusion region is connected to one of a high-potential power supply and a low-potential power supply, the second diffusion region is connected to the input terminal, and the semiconductor region is connected to another power supply having a voltage high enough to reverse bias the junction between the semiconductor region and the first diffusion region.
摘要翻译：公开了一种具有扩展的输入电压推荐条件范围的半导体器件。在实施例中，在其输入端子上具有输入保护的半导体器件包括：具有限定在半导体区域中并且分别具有第二导电类型的第一导电类型，第一和第二扩散区域的半导体区域，以及通过使用作为基底的半导体区域，第一扩散区域作为集电极，第二扩散区域作为发射极。第一扩散区域连接到高电位电源和低电位电源中的一个，第二扩散区域连接到输入端子，并且半导体区域连接到具有足够高的电压的另一个电源，反向偏置半导体区域和第一扩散区域之间的结。

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