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1. 发明授权

US4587639A Static semiconductor memory device incorporating redundancy memory cells 失效
标题翻译：结合冗余存储单元的静态半导体存储器件
公开(公告)号：US4587639A
公开(公告)日：1986-05-06
申请号：US593771
申请日：1984-03-27
申请人： Keizo Aoyama , Teruo Seki , Takahiko Yamauchi
发明人： Keizo Aoyama , Teruo Seki , Takahiko Yamauchi
IPC分类号： G11C7/12 , G11C8/18 , G11C11/419 , G11C29/00 , G11C7/00
CPC分类号： G11C29/83 , G11C11/419 , G11C29/832 , G11C7/12 , G11C8/18
摘要： In a static semiconductor memory device incorporating redundancy memory cells (C.sub.R0, C.sub.R1, . . . ), a connecting/disconnecting circuit is linked between a power supply terminal (V.sub.CC) and one of bit lines (B.sub.0, B.sub.0, . . . ), thereby reducing or cutting off a current flowing through a defective memory cell.
摘要翻译：在包含冗余存储单元（CR0，CR1 ...）的静态半导体存储器件中，连接/断开电路连接在电源端（VCC）和位线（B0，＆amp; B和...之一）之间，从而减少或切断流经缺陷存储单元的电流。

2. 发明授权

US4549199A Semiconductor device providing a contact structure which can be miniaturized 失效
标题翻译：提供可以小型化的接触结构的半导体器件
公开(公告)号：US4549199A
公开(公告)日：1985-10-22
申请号：US513611
申请日：1983-07-14
申请人： Takahiko Yamauchi , Teruo Seki , Keizo Aoyama
发明人： Takahiko Yamauchi , Teruo Seki , Keizo Aoyama
IPC分类号： H01L23/522 , H01L21/768 , H01L23/485 , H01L23/48 , H01L29/04 , H01L29/06
CPC分类号： H01L23/485 , H01L21/76895 , H01L2924/0002 , H01L2924/3011
摘要： A semiconductor device comprises a connection structure composed of a first conductive layer formed in or on a semiconductor substrate, a second conductive layer arranged adjacent to the first conductive layer, and a third conductive layer connecting the first conductive layer to the second conductive layer. The device of the present invention provides a contact structure which can be miniaturized.
摘要翻译：半导体器件包括由半导体衬底中或其上形成的第一导电层，与第一导电层相邻布置的第二导电层和将第一导电层连接到第二导电层的第三导电层构成的连接结构。本发明的装置提供可以小型化的接触结构。

3. 发明授权

US4571510A Decoder circuit 失效
标题翻译：解码电路
公开(公告)号：US4571510A
公开(公告)日：1986-02-18
申请号：US535831
申请日：1983-09-26
申请人： Teruo Seki , Takahiko Yamauchi , Keizo Aoyama
发明人： Teruo Seki , Takahiko Yamauchi , Keizo Aoyama
IPC分类号： G11C11/413 , G11C8/10 , H03K19/20 , G11C8/00 , H03K19/017 , H03K19/096
CPC分类号： G11C8/10
摘要： A decoder circuit receives decoder inputs and producing decoder outputs. The decoder inputs are applied, as control inputs, to respective input transistors connected in parallel with each other. The outputs thereof are commonly connected to a node. The node is connected to a gate transistor and latch transistors. The gate transistor is operative to invert the level at the node momentarily every time the decoder circuit is switched from a nonselection state to a selection state. The latch transistors maintain the level at the node as the decoder output level.
摘要翻译：解码器电路接收解码器输入并产生解码器输出。解码器输入作为控制输入施加到彼此并联的相应输入晶体管。其输出通常连接到节点。节点连接到栅极晶体管和锁存晶体管。每当解码器电路从非选择状态切换到选择状态时，栅极晶体管可操作地反转节点处的电平。锁存晶体管将节点处的电平保持为解码器输出电平。

4. 发明授权

US4809046A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4809046A
公开(公告)日：1989-02-28
申请号：US915967
申请日：1986-10-06
申请人： Keizo Aoyama , Takahiko Yamauchi , Teruo Seki
发明人： Keizo Aoyama , Takahiko Yamauchi , Teruo Seki
IPC分类号： G11C5/00 , G11C5/06 , G11C5/14 , G11C11/412 , H01L23/556 , H01L27/11 , H01L27/02
CPC分类号： G11C5/063 , G11C11/4125 , G11C5/005 , G11C5/14 , H01L23/556 , H01L27/1112 , H01L2924/0002 , Y10S257/927
摘要： A static-type semiconductor memory device having a three-layer structure: gate-electrode wiring lines being formed from a first conductive layer of, for example, polycrystalline silicon; word lines, ground lines, and power supply lines being formed from a second conductive layer of, for example, aluminum; and bit lines being formed from a third conductive layer of, for example, aluminum. The bit lines extending in a column direction, and the ground lines extending in a row direction. Thus, providing an improved degree of integration, an improved operating speed, an improved manufacturing yield, and a countermeasure for soft errors due to alpha particles.
摘要翻译：一种具有三层结构的静电型半导体存储器件：由例如多晶硅的第一导电层形成的栅电极布线; 字线，接地线和电源线由例如铝的第二导电层形成; 并且位线由例如铝的第三导电层形成。位线沿列方向延伸，接地线沿行方向延伸。因此，提供改进的集成度，改进的操作速度，改进的制造产量以及由于α粒子导致的软误差的对策。

5. 发明授权

US4581549A CMIS chip-select circuit 失效
标题翻译： CMIS芯片选择电路
公开(公告)号：US4581549A
公开(公告)日：1986-04-08
申请号：US535833
申请日：1983-09-26
申请人： Keizo Aoyama , Takahiko Yamauchi , Teruo Seki
发明人： Keizo Aoyama , Takahiko Yamauchi , Teruo Seki
IPC分类号： H03K19/0948 , G11C8/18 , H03K19/00 , H03K19/096 , H03K17/693
CPC分类号： H03K19/0016 , G11C8/18 , H03K19/0963
摘要： A CMIS circuit device such as an IC chip in a semiconductor memory device, is made selectable by using at least two chip-select signals having opposite polarities. The CMIS circuit device has a chip-select control circuit for establishing a chip-selected state or a chip-unselected state upon receiving the abovementioned chip-select signals. The chip-select control circuit includes a CMIS inverter circuit which inverts one of the chip-select signals, and a CMIS logic gate circuit which receives an output signal from the CMIS inverter circuit and the other chip select signal or signals and outputs an internal chip-select control signal. The CMIS inverter circuit includes a CMIS inverter and one or more control transistors which receive the other chip-select signal or signals at the gates thereof and which are inserted in series between a power terminal of the CMIS inverter and a power source.
摘要翻译：通过使用具有相反极性的至少两个芯片选择信号，可以选择诸如半导体存储器件中的IC芯片的CMIS电路器件。 CMIS电路装置具有芯片选择控制电路，用于在接收上述芯片选择信号时建立芯片选择状态或芯片未选择状态。芯片选择控制电路包括使芯片选择信号中的一个反相的CMIS反相器电路和从CMIS反相器电路接收输出信号的CMIS逻辑门电路和另一个芯片选择信号或信号，并输出内部芯片 - 选择控制信号。 CMIS逆变器电路包括CMIS反相器和一个或多个控制晶体管，其在其栅极处接收另一个芯片选择信号或信号，并且串联插入在CMIS反相器的电源端子和电源之间。

6. 发明授权

US4573147A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4573147A
公开(公告)日：1986-02-25
申请号：US478722
申请日：1983-03-25
申请人： Keizo Aoyama , Takahiko Yamauchi , Teruo Seki
发明人： Keizo Aoyama , Takahiko Yamauchi , Teruo Seki
IPC分类号： G11C7/00 , G11C7/10 , G11C8/00 , G11C8/18 , G11C11/409 , G11C11/419 , G11C11/40
CPC分类号： G11C7/106 , G11C11/419 , G11C7/1051 , G11C8/00 , G11C8/18
摘要： A semiconductor memory device such as a static-type random-access memory device includes an address-change detection circuit which generates a pulse signal when an input address signal has changed and a latch circuit which temporarily stores the readout signal from the selected memory cell. The readout signal is input into the latch circuit in synchronization with the timing of the pulse signal or a short time after the pulse signal, and the readout data from the semiconductor memory device is obtained from the latch circuit, thereby increasing the time interval during which the readout data from the semiconductor memory device is available.
摘要翻译：诸如静态型随机存取存储器件的半导体存储器件包括地址变化检测电路，其在输入地址信号已经改变时产生脉冲信号，以及临时存储来自所选存储单元的读出信号的锁存电路。读出信号与脉冲信号的定时或脉冲信号之后的短时间同步地输入到锁存电路中，并且从锁存电路获得来自半导体存储器件的读出数据，从而增加其间的时间间隔来自半导体存储器件的读出数据可用。

7. 发明授权

US4563754A Static-type random-access memory device 失效
标题翻译：静态型随机存取存储器件
公开(公告)号：US4563754A
公开(公告)日：1986-01-07
申请号：US480582
申请日：1983-03-30
申请人： Keizo Aoyama , Takahiko Yamauchi , Teruo Seki
发明人： Keizo Aoyama , Takahiko Yamauchi , Teruo Seki
IPC分类号： G11C11/412 , G11C11/41 , G11C11/413 , G11C11/418 , G11C11/419 , H01L21/8244 , H01L27/11 , G11C7/00
CPC分类号： G11C11/419 , G11C11/418
摘要： A static-type RAM device in which the amplitude of the data signal stored in a memory cell just after the writing in of data is completed is increased and the stability of the data stored in each memory cell is increased. The RAM device includes a bit-line pulling-up circuit for pulling up the potential of a bit line to a voltage which is approximately equal to or larger than the power supply voltage and a word-line pulling-up circuit for pulling up the potential of a selected word line to a voltage which is larger than the power supply voltage after the writing in of data is completed.
摘要翻译：静态型RAM装置，其中刚刚在数据写入之后存储在存储单元中的数据信号的幅度增加，并且存储在每个存储单元中的数据的稳定性增加。 RAM装置包括用于将位线的电位提升到大致等于或大于电源电压的电压的位线上拉电路和用于提高电位的字线上拉电路所选择的字线的数据写入数据之后的电压大于电源电压。

8. 发明授权

US4603404A Semiconductor memory device with redundant cells 失效
标题翻译：具有冗余单元的半导体存储器件
公开(公告)号：US4603404A
公开(公告)日：1986-07-29
申请号：US453575
申请日：1982-12-27
申请人： Takahiko Yamauchi , Teruo Seki , Keizo Aoyama
发明人： Takahiko Yamauchi , Teruo Seki , Keizo Aoyama
IPC分类号： G11C17/00 , G11C29/00 , G11C29/04 , G11C7/00
CPC分类号： G11C29/846
摘要： A semiconductor memory device in which the memory cells are arranged in matrix form and in which, when a defective cell exists among the memory cells and a row or column containing the defective cell is selected, the selected row or column is switched to a predetermined redundant row or a predetermined redundant column additionally and independently provided. A plurality of switching circuits are provided, each of the switching circuits being connected to the output of the decoder circuit, which select the row or the column of memory cells. A fusing circuit is connected to each of the switching circuits, and when the fuse in the fusing circuit is disconnected, the row or the column containing the defective cell is switched to the redundant row or the redundant column.
摘要翻译：一种半导体存储器件，其中存储器单元以矩阵形式布置，并且当存储器单元中存在缺陷单元并且选择了包含缺陷单元的行或列时，将所选择的行或列切换到预定的冗余行或预定的冗余列。提供多个开关电路，每个开关电路连接到选择存储单元的行或列的解码器电路的输出。熔断电路连接到每个开关电路，并且当熔断电路中的熔丝断开时，包含有缺陷单元的列或列被切换到冗余行或冗余列。

9. 发明授权

US4507574A Constant operation speed logic circuit 失效
标题翻译：恒定运行速度逻辑电路
公开(公告)号：US4507574A
公开(公告)日：1985-03-26
申请号：US449767
申请日：1982-12-14
申请人： Teruo Seki , Takahiko Yamauchi , Keizo Aoyama
发明人： Teruo Seki , Takahiko Yamauchi , Keizo Aoyama
IPC分类号： H03K19/0948 , G11C8/08 , G11C8/10 , G11C8/18 , G11C11/418 , H03K19/017 , H03K19/0944 , H03K19/094 , H03K19/096
CPC分类号： H03K19/09443 , G11C11/418 , G11C8/08 , G11C8/10 , G11C8/18 , H03K19/017
摘要： A logic circuit includes a plurality of input terminals (IN.sub.1, IN.sub.2, . . . ), an output terminal (OUT), a load (L), and at least two driver circuits (D.sub.1, D.sub.2, . . . ). Each of the driver circuits includes a plurality of gates connected in series, each gate being driven by one of the potentials at the input terminals. In addition, the first gates (Q.sub.11, Q.sub.22, . . . or Q.sub.11 ', Q.sub.22 ', . . . ) of the driver circuit connected directly to the output terminal are driven by different potentials at the input terminals.
摘要翻译：逻辑电路包括多个输入端子（IN1，IN2 ...），输出端子（OUT），负载（L）和至少两个驱动器电路（D1，D2 ...）。每个驱动器电路包括串联连接的多个栅极，每个栅极由输入端子中的一个电位驱动。此外，直接连接到输出端子的驱动电路的第一个门（Q11，Q22，...或Q11'，Q22'，...）由输入端的不同电位驱动。

10. 发明授权

US4449066A Buffer circuit for generating output signals having short recovery time 失效
标题翻译：用于产生具有短恢复时间的输出信号的缓冲电路
公开(公告)号：US4449066A
公开(公告)日：1984-05-15
申请号：US331287
申请日：1981-12-16
申请人： Keizo Aoyama , Takahiko Yamauchi
发明人： Keizo Aoyama , Takahiko Yamauchi
IPC分类号： H03K19/0948 , H03K5/02 , H03K17/06 , H03K17/687 , H03K19/017 , H03K19/094 , H03K17/10
CPC分类号： H03K19/017 , H03K19/01714 , H03K5/023
摘要： In a buffer circuit comprising a first, a second and a third transistor and a capacitor for bootstrap action, an inverter is connected to the output point at which the second and third transistors are connected in series, the inverter inverting the potential of the output point and supplying the inverted potential to the gate of the first transistor, thereby ensuring the quick rise of the leading edge of the output signal.
摘要翻译：在包括第一，第二和第三晶体管和用于自举动作的电容器的缓冲电路中，反相器连接到串联连接第二和第三晶体管的输出点，反相器反转输出点的电位并将反相电位提供给第一晶体管的栅极，从而确保输出信号的前沿的快速上升。

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