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    • 8. 发明授权
    • Synchronous communication interface for reducing the effect of data
processor latency
    • 同步通信接口,用于减少数据处理器延迟的影响
    • US5228129A
    • 1993-07-13
    • US519263
    • 1990-05-02
    • Stewart F. BryantMichael Harwood
    • Stewart F. BryantMichael Harwood
    • G06F13/28G06F13/38
    • G06F13/38G06F13/28
    • Incoming data which is required to be passed to a desired storage location under the control of a processor is received by a store prior to being passed to a serial communications controller. The store is preferably a FIFO store and stores the data at an incoming data rate determined by the incoming transmission line data rate and feeds the data to the serial communications controller at a higher data rate under the control of a clock generator which is energized by control circuitry only when the serial communications controller indicates that it is able to accept the data. The processor can therefore control the serial communications controller to cease to process incoming data, which data is then stored until the processor can spare the time to recommence processing the incoming data.
    • 在处理器的控制下需要传递到期望的存储位置的传入数据在被传送到串行通信控制器之前由存储器接收。 存储器优选地是FIFO存储器,并且以由输入传输线数据速率确定的输入数据速率存储数据,并且在由控制器激励的时钟发生器的控制下以更高的数据速率将数据馈送到串行通信控制器 只有当串行通信控制器指示它能够接受数据时,才能使用电路。 因此,处理器可以控制串行通信控制器停止处理输入数据,然后存储数据,直到处理器可以节省重新开始处理输入数据的时间。