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1. 发明授权

US06587912B2 Method and apparatus for implementing multiple memory buses on a memory module 有权
标题翻译：用于在存储器模块上实现多个存储器总线的方法和装置
公开(公告)号：US06587912B2
公开(公告)日：2003-07-01
申请号：US09163860
申请日：1998-09-30
申请人： Michael W. Leddige , Bryce D. Horine , Randy Bonella , Peter D. MacWilliams
发明人： Michael W. Leddige , Bryce D. Horine , Randy Bonella , Peter D. MacWilliams
IPC分类号： G06F1200
CPC分类号： G06F13/4256
摘要： A computer system memory module includes a bi-directional repeater hub that in a first direction takes as an input a memory bus signal in a first port, regenerates the memory signals, and outputs the regenerated memory signal at a second port as at least one separate signal for coupling to a memory bus for each of the regenerated separate signals. In a second direction, the bi-directional repeater hub takes as input at least one memory bus signal at the second port, regenerates each input memory bus signal, and outputs the regenerated memory signal at the first port for coupling to a memory bus.
摘要翻译：计算机系统存储器模块包括双向中继器集线器，其在第一方向上将第一端口中的存储器总线信号作为输入，再生存储器信号，并将第二端口处的再生存储器信号作为至少一个单独的信号，用于耦合到存储器总线，用于每个再生的分离信号。在第二方向上，双向中继器集线器将第二端口处的至少一个存储器总线信号作为输入，再生每个输入存储器总线信号，并在第一端口处输出再生的存储器信号以耦合到存储器总线。

2. 发明授权

US06477614B1 Method for implementing multiple memory buses on a memory module 有权
标题翻译：在存储器模块上实现多个存储器总线的方法
公开(公告)号：US06477614B1
公开(公告)日：2002-11-05
申请号：US09658293
申请日：2000-09-08
申请人： Michael W. Leddige , Bryce D. Horine , Randy Bonella , Peter D. MacWilliams
发明人： Michael W. Leddige , Bryce D. Horine , Randy Bonella , Peter D. MacWilliams
IPC分类号： G06F1206
CPC分类号： G06F13/4256
摘要： A computer system memory module includes a bi-directional repeater hub that in a first direction takes as an input a memory bus signal in a first port, regenerates the memory signals, and outputs the regenerated memory signal at a second port as at least one separate signal for coupling to a memory bus for each of the regenerated separate signals. In a second direction, the bi-directional repeater hub takes as input at least one memory bus signal at the second port, regenerates each input memory bus signal, and outputs the regenerated memory signal at the first port for coupling to a memory bus. A method includes determining whether a memory device to which signals are addressed is on a first memory module. Signals are routed to a first memory bus on the first memory module connected to the memory device if the memory is on the first memory module. Signals are routed to a second memory bus on a second memory module if the memory device is not on the first memory module.
摘要翻译：计算机系统存储器模块包括双向中继器集线器，其在第一方向上将第一端口中的存储器总线信号作为输入，再生存储器信号，并将第二端口处的再生存储器信号作为至少一个单独的信号，用于耦合到存储器总线，用于每个再生的分离信号。在第二方向上，双向中继器集线器在第二端口处输入至少一个存储器总线信号，再生每个输入存储器总线信号，并在第一端口处输出再生的存储器信号以耦合到存储器总线。一种方法包括确定信号被寻址的存储器件是否在第一存储器模块上。如果存储器位于第一存储器模块上，则信号被路由到连接到存储器设备的第一存储器模块上的第一存储器总线。如果存储设备不在第一个存储器模块上，则信号被路由到第二存储器模块上的第二存储器总线。

3. 发明授权

US06369605B1 Self-terminated driver to prevent signal reflections of transmissions between electronic devices 有权
标题翻译：自终端驱动器，以防止电子设备之间传输的信号反射
公开(公告)号：US06369605B1
公开(公告)日：2002-04-09
申请号：US09664994
申请日：2000-09-18
申请人： Randy Bonella , John Halbert
发明人： Randy Bonella , John Halbert
IPC分类号： H03K1716
CPC分类号： H03K19/018585
摘要： An output driver circuit within an electronic device to provide a configurable driver circuit. When placed in a first mode of operation, the driver circuit drives an output signal. When placed in a second mode of operation, the driver circuit provides impedance matching to prevent signal reflection.
摘要翻译：电子设备内的输出驱动器电路，用于提供可配置的驱动电路。当处于第一操作模式时，驱动器电路驱动输出信号。当处于第二操作模式时，驱动电路提供阻抗匹配以防止信号反射。

4. 发明申请

US20070136523A1 Advanced dynamic disk memory module special operations 审中-公开
标题翻译：高级动态磁盘内存模块专用操作
公开(公告)号：US20070136523A1
公开(公告)日：2007-06-14
申请号：US11635926
申请日：2006-12-08
申请人： Randy Bonella , Chung Lam
发明人： Randy Bonella , Chung Lam
IPC分类号： G06F13/00
CPC分类号： G06F12/0866 , G06F9/4401 , G06F2212/2022 , G06F2212/2112 , G06F2212/2515
摘要： A memory module including a volatile memory, a non-volatile memory, and a controller that provides address, data, and control interfaces to the memories and to a host system, such as, for example, a personal computer, is operable to interact with the host system so as to provide one or more additional layers in the memory hierarchy of the host system. In one aspect of the present invention the controller operates the volatile memory of the memory module as a cache for the non-volatile memory of the memory module. In another aspect of the present invention data representing one or more software applications and/or one or more data sets are stored in the non-volatile memory of the memory module along with security information such that a host system may quickly launch applications from the memory module rather than from a slower hard disk drive.
摘要翻译：包括易失性存储器，非易失性存储器和向存储器和主机系统（例如个人计算机）提供地址，数据和控制接口的控制器的存储器模块可操作以与主机系统，以便在主机系统的存储器层级中提供一个或多个附加层。在本发明的一个方面，控制器将存储器模块的易失性存储器作为存储器模块的非易失性存储器的缓存器进行操作。在本发明的另一方面，代表一个或多个软件应用和/或一个或多个数据集的数据与安全信息一起存储在存储器模块的非易失性存储器中，使得主机系统可以从存储器快速启动应用模块，而不是从较慢的硬盘驱动器。

5. 发明申请

US20070079065A1 Advanced dynamic disk memory module 失效
标题翻译：高级动态磁盘内存模块
公开(公告)号：US20070079065A1
公开(公告)日：2007-04-05
申请号：US11453293
申请日：2006-06-13
申请人： Randy Bonella , Chung Lam
发明人： Randy Bonella , Chung Lam
IPC分类号： G06F13/00 , G06F12/00
CPC分类号： G06F13/405
摘要： Memory modules address the growing gap between main memory performance and disk drive performance in computational apparatus such as personal computers. Memory modules disclosed herein fill the need for substantially higher storage capacity in end-user add-in memory modules. Such memory modules accelerate the availability of applications, and data for those applications. An exemplary application of such memory modules is as a high capacity consumer memory product that can be used in Hi-Definition video recorders. In various embodiments, memory modules include a volatile memory, a non-volatile memory, and a command interpreter that includes interfaces to the memories and to various busses. The first memory acts as an accelerating buffer for the second memory, and the second memory provides non-volatile backup for the first memory. In some embodiments data transfer from the first memory to the second memory may be interrupted to provide read access to the second memory.
摘要翻译：存储器模块解决了诸如个人计算机之类的计算设备中主存储器性能和磁盘驱动器性能之间日益增长的差距。本文公开的存储器模块填补了在最终用户加载存储器模块中的显着更高的存储容量的需求。这些内存模块可加速应用程序的可用性以及这些应用程序的数据。这种存储器模块的示例性应用是可用于高清晰度录像机的高容量消费者存储产品。在各种实施例中，存储器模块包括易失性存储器，非易失性存储器和包括到存储器和各种总线的接口的命令解释器。第一存储器用作第二存储器的加速缓冲器，并且第二存储器为第一存储器提供非易失性备份。在一些实施例中，可以中断从第一存储器到第二存储器的数据传输，以提供对第二存储器的读取访问。

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