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1. 发明申请

US20070284656A1 Conductive hard mask to protect patterned features during trench etch 失效
标题翻译：导电硬掩模，用于在沟槽蚀刻期间保护图案特征
公开(公告)号：US20070284656A1
公开(公告)日：2007-12-13
申请号：US11444936
申请日：2006-05-31
申请人： Steven J. Radigan , Usha Raghuram , Samuel V. Dunton , Michael W. Konevecki
发明人： Steven J. Radigan , Usha Raghuram , Samuel V. Dunton , Michael W. Konevecki
IPC分类号： H01L29/76 , H01L21/8234
CPC分类号： H01L23/5252 , H01L27/1021 , H01L29/6609 , H01L2924/0002 , H01L2924/00
摘要： A method is provided for forming patterned features using a conductive hard mask, where the conductive hard mask protects those features during a subsequent trench etch to form Damascene conductors providing electrical connection to those features from above. The thickness of the hard mask provides a margin to avoid overetch during the trench etch which may be harmful to device performance. The method is advantageously used in formation of a monolithic three dimensional memory array.
摘要翻译：提供了一种使用导电硬掩模形成图案化特征的方法，其中导电硬掩模在随后的沟槽蚀刻期间保护这些特征以形成提供从上方到那些特征的电连接的大马士革导体。硬掩模的厚度提供了一个余量，以避免在沟槽蚀刻期间的过蚀刻，这可能对器件性能有害。该方法有利地用于形成单片三维存储器阵列。

2. 发明申请

US20090273022A1 CONDUCTIVE HARD MASK TO PROTECT PATTERNED FEATURES DURING TRENCH ETCH 审中-公开
标题翻译：导电硬掩模，以保护在TRENCH ETCH期间的图案特征
公开(公告)号：US20090273022A1
公开(公告)日：2009-11-05
申请号：US12502796
申请日：2009-07-14
申请人： Steven J. Radigan , Usha Raghuram , Samuel V. Dunton , Michael W. Konevecki
发明人： Steven J. Radigan , Usha Raghuram , Samuel V. Dunton , Michael W. Konevecki
IPC分类号： H01L27/105 , H01L21/8234 , H01L21/822 , H01L27/06
CPC分类号： H01L23/5252 , H01L27/1021 , H01L29/6609 , H01L2924/0002 , H01L2924/00
摘要： A monolithic three dimensional memory array is formed by a method that includes forming a first memory level above a substrate by i) forming a plurality of first substantially parallel conductors extending in a first direction, ii) forming first pillars above the first conductors, each first pillar comprising a first conductive layer or layerstack above a vertically oriented diode, the first pillars formed in a single photolithography step, iii) depositing a first dielectric layer above the first pillars, and iv) etching a plurality of substantially parallel first trenches in the first dielectric layer, the first trenches extending in a second direction, wherein, after the etching step, the lowest point in the trenches is above the lowest point of the first conductive layer or layerstack, wherein the first conductive layer or layerstack does not comprise a resistivity-switching metal oxide or nitride. The method also includes monolithically forming a second memory level above the first memory level. Other aspects are also described.
摘要翻译：单片三维存储器阵列通过一种方法形成，该方法包括通过在第一方向上形成多个沿第一方向延伸的多个第一基本上平行的导体形成第一存储器电平，ii）在第一导体上方形成第一柱，柱，其包括在垂直取向的二极管上方的第一导电层或层堆叠，在单个光刻步骤中形成的第一柱，iii）在第一柱上方沉积第一电介质层，以及iv）在第一栅极中蚀刻多个基本上平行的第一沟槽所述第一沟槽在第二方向上延伸，其中在所述蚀刻步骤之后，所述沟槽中的最低点高于所述第一导电层或层堆叠的最低点，其中所述第一导电层或所述层堆叠不包含电阻率开关金属氧化物或氮化物。该方法还包括在第一存储器级上方单片地形成第二存储器级。还描述了其他方面。

3. 发明授权

US07300876B2 Method for cleaning slurry particles from a surface polished by chemical mechanical polishing 失效
标题翻译：通过化学机械抛光抛光的表面清洗浆料颗粒的方法
公开(公告)号：US07300876B2
公开(公告)日：2007-11-27
申请号：US11013067
申请日：2004-12-14
申请人： Samuel V. Dunton , Steven J. Radigan
发明人： Samuel V. Dunton , Steven J. Radigan
IPC分类号： H01L21/302
CPC分类号： H01L21/76819 , H01L21/02065 , H01L21/31053 , H01L21/3212 , H01L21/7684 , H01L27/101 , H01L27/1021 , Y10S438/959
摘要： A method is provided to clean slurry particles from a surface in which tungsten and dielectric are coexposed after a dielectric CMP step. Such a surface is formed when tungsten features are patterned and etched, the tungsten features are covered with dielectric, and the dielectric is planarized to expose tops of the tungsten features. The surface to be cleaned is subjected to mechanical action in an acid environment. Suitable mechanical action includes performing a brief tungsten CMP step on the tungsten features or scrubbing the surface using, for example, a commercial post-CMP scrubber.
摘要翻译：提供了一种方法，用于在电介质CMP步骤之后从其中钨和电介质共面的表面清洗浆料颗粒。当钨特征被图案化和蚀刻时，形成这样的表面，钨特征被电介质覆盖，并且电介质被平坦化以暴露钨特征的顶部。待清洁的表面在酸性环境中受到机械作用。合适的机械作用包括使用例如商业后CMP洗涤器在钨特征上进行简单的钨CMP步骤或擦洗表面。

4. 发明申请

US20090085087A1 LINER FOR TUNGSTEN/SILICON DIOXIDE INTERFACE IN MEMORY 有权
标题翻译：内存中的TUNGSTEN /二氧化硅界面
公开(公告)号：US20090085087A1
公开(公告)日：2009-04-02
申请号：US11863734
申请日：2007-09-28
申请人： Yoichiro Tanaka , Steven J. Radigan , Usha Raghuram
发明人： Yoichiro Tanaka , Steven J. Radigan , Usha Raghuram
IPC分类号： H01L29/788 , H01L21/4763
CPC分类号： H01L27/101 , H01L27/1021
摘要： A semiconductor wafer assembly includes a base of dielectric. A layer of silicon is deposited thereover. A metal hard mask is deposited over the silicon. A dielectric hard mask is deposited over the metal hard mask. Photoresist is deposited over the dielectric hard mask, whereby a plurality of sacrificial columns is formed from the layer of metal hard mask through the photoresist such that the sacrificial columns extend out from the silicon layer. An interface layer is disposed between the layer of conductive material and the layer of hard mask to enhance adhesion between each of the plurality of sacrificial columns and the layer of conductive material to optimize the formation of junction diodes out of the silicon by preventing the plurality of sacrificial columns from being detached from the layer of silicon prematurely due to the sacrificial columns peeling or falling off.
摘要翻译：半导体晶片组件包括电介质基体。一层硅沉积在其上。金属硬掩模沉积在硅上。在金属硬掩模上沉积电介质硬掩模。光致抗蚀剂沉积在电介质硬掩模上，由此通过光致抗蚀剂从金属硬掩模层形成多个牺牲柱，使得牺牲柱从硅层延伸出来。界面层设置在导电材料层和硬掩模层之间，以增强多个牺牲柱和导电材料层之间的粘附力，以通过防止多个牺牲柱由于牺牲柱脱落或脱落而过早地与硅层分离。

5. 发明授权

US08071475B2 Liner for tungsten/silicon dioxide interface in memory 有权
标题翻译：内存中用于钨/二氧化硅界面的衬垫
公开(公告)号：US08071475B2
公开(公告)日：2011-12-06
申请号：US11863734
申请日：2007-09-28
申请人： Yoichiro Tanaka , Steven J. Radigan , Usha Raghuram
发明人： Yoichiro Tanaka , Steven J. Radigan , Usha Raghuram
IPC分类号： H01L21/44
CPC分类号： H01L27/101 , H01L27/1021
摘要： A semiconductor wafer assembly includes a base of dielectric. A layer of silicon is deposited thereover. A metal hard mask is deposited over the silicon. A dielectric hard mask is deposited over the metal hard mask. Photoresist is deposited over the dielectric hard mask, whereby a plurality of sacrificial columns is formed from the layer of metal hard mask through the photoresist such that the sacrificial columns extend out from the silicon layer. An interface layer is disposed between the layer of conductive material and the layer of hard mask to enhance adhesion between each of the plurality of sacrificial columns and the layer of conductive material to optimize the formation of junction diodes out of the silicon by preventing the plurality of sacrificial columns from being detached from the layer of silicon prematurely due to the sacrificial columns peeling or falling off.
摘要翻译：半导体晶片组件包括电介质基体。一层硅沉积在其上。金属硬掩模沉积在硅上。电介质硬掩模沉积在金属硬掩模上。光致抗蚀剂沉积在电介质硬掩模上，由此通过光致抗蚀剂从金属硬掩模层形成多个牺牲柱，使得牺牲柱从硅层延伸出来。界面层设置在导电材料层和硬掩模层之间，以增强多个牺牲柱和导电材料层之间的粘附力，以通过防止多个牺牲柱由于牺牲柱脱落或脱落而过早地与硅层分离。

6. 发明授权

US07718546B2 Method for fabricating a 3-D integrated circuit using a hard mask of silicon-oxynitride on amorphous carbon 有权
标题翻译：使用无定形碳上的氮氧化硅硬掩模制造3-D集成电路的方法
公开(公告)号：US07718546B2
公开(公告)日：2010-05-18
申请号：US11769027
申请日：2007-06-27
申请人： Steven J. Radigan , Michael W. Konevecki
发明人： Steven J. Radigan , Michael W. Konevecki
IPC分类号： H01L21/469
CPC分类号： H01L27/1021 , H01L23/5252 , H01L27/0688 , H01L29/8615 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a 3-D monolithic memory device. Silicon-oxynitride (SixOyNz) on amorphous carbon is used an effective, easily removable hard mask with high selectivity to silicon, oxide, and tungsten. A silicon-oxynitride layer is etched using a photoresist layer, and the resulting etched SixOyNz layer is used to etch an amorphous carbon layer. Silicon, oxide, and/or tungsten layers are etched using the amorphous carbon layer. In one implementation, conductive rails of the 3-D monolithic memory device are formed by etching an oxide layer such as silicon dioxide (SiO2) using the patterned amorphous carbon layer as a hard mask. Memory cell diodes are formed as pillars in polysilicon between the conductive rails by etching a polysilicon layer using another patterned amorphous carbon layer as a hard mask. Additional levels of conductive rails and memory cell diodes are formed similarly to build the 3-D monolithic memory device.
摘要翻译：一种用于制造3-D单片存储器件的方法。无定形碳上的氮氧化硅（SixOyNz）被用于对硅，氧化物和钨具有高选择性的有效的，容易移除的硬掩模。使用光致抗蚀剂层蚀刻硅 - 氧氮化物层，并且使用所得到的蚀刻的六方氮化物层来蚀刻无定形碳层。使用无定形碳层蚀刻硅，氧化物和/或钨层。在一个实施方案中，通过使用图案化的非晶碳层作为硬掩模来蚀刻诸如二氧化硅（SiO 2）的氧化物层来形成3-D单片存储器件的导电轨道。通过使用另一图案化的非晶碳层作为硬掩模蚀刻多晶硅层，在导电轨道之间的多晶硅中形成存储单元二极管。与构建3-D单片存储器件类似地形成附加电平的导电轨和存储单元二极管。

7. 发明申请

US20090004786A1 METHOD FOR FABRICATING A 3-D INTEGRATED CIRCUIT USING A HARD MASK OF SILICON-OXYNITRIDE ON AMORPHOUS CARBON 有权
标题翻译：使用硅氧烷在非晶碳上的硬掩模制造三维集成电路的方法
公开(公告)号：US20090004786A1
公开(公告)日：2009-01-01
申请号：US11769027
申请日：2007-06-27
申请人： Steven J. Radigan , Michael W. Konevecki
发明人： Steven J. Radigan , Michael W. Konevecki
IPC分类号： H01L21/82
CPC分类号： H01L27/1021 , H01L23/5252 , H01L27/0688 , H01L29/8615 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a 3-D monolithic memory device. Silicon-oxynitride (SixOyNz) on amorphous carbon is used an effective, easily removable hard mask with high selectivity to silicon, oxide, and tungsten. A silicon-oxynitride layer is etched using a photoresist layer, and the resulting etched SixOyNz layer is used to etch an amorphous carbon layer. Silicon, oxide, and/or tungsten layers are etched using the amorphous carbon layer. In one implementation, conductive rails of the 3-D monolithic memory device are formed by etching an oxide layer such as silicon dioxide (SiO2) using the patterned amorphous carbon layer as a hard mask. Memory cell diodes are formed as pillars in polysilicon between the conductive rails by etching a polysilicon layer using another patterned amorphous carbon layer as a hard mask. Additional levels of conductive rails and memory cell diodes are formed similarly to build the 3-D monolithic memory device.
摘要翻译：一种用于制造3-D单片存储器件的方法。无定形碳上的氮氧化硅（SixOyNz）被用于对硅，氧化物和钨具有高选择性的有效的，容易移除的硬掩模。使用光致抗蚀剂层蚀刻硅 - 氧氮化物层，并且使用所得到的蚀刻的六方氮化物层来蚀刻无定形碳层。使用无定形碳层蚀刻硅，氧化物和/或钨层。在一个实施方案中，通过使用图案化的非晶碳层作为硬掩模来蚀刻诸如二氧化硅（SiO 2）的氧化物层来形成3-D单片存储器件的导电轨道。通过使用另一图案化的非晶碳层作为硬掩模蚀刻多晶硅层，在导电轨道之间的多晶硅中形成存储单元二极管。与构建3-D单片存储器件类似地形成附加电平的导电轨和存储单元二极管。

8. 发明申请

US20100243602A1 IMAGING POST STRUCTURES USING X AND Y DIPOLE OPTICS AND A SINGLE MASK 有权
标题翻译：使用X和Y DIPOLE OPTICS和单个掩模成像后结构
公开(公告)号：US20100243602A1
公开(公告)日：2010-09-30
申请号：US12796449
申请日：2010-06-08
申请人： Yung-Tin Chen , Steven J. Radigan , Paul Poon , Michael W. Konevecki
发明人： Yung-Tin Chen , Steven J. Radigan , Paul Poon , Michael W. Konevecki
IPC分类号： C23F1/00
CPC分类号： G03F7/70466 , G03F1/00 , G03F7/70425
摘要： A photolithographic method uses different exposure patterns. In one aspect, a photo-sensitive layer on a substrate is subject to a first exposure using optics having a first exposure pattern, such as an x-dipole pattern, followed by exposure using optics having a second exposure pattern, such as a y-dipole pattern, via the same mask, and with the photo-sensitive layer fixed relative to the mask. A 2-D post pattern with a pitch of approximately 70-150 nm may be formed in a layer beneath the photo-sensitive layer using 157-193 nm UV light, and hyper-numerical aperture optics, in one approach. In another aspect, hard baking is performed after both of the first and second exposures to erase a memory effect of photoresist after the first exposure. In another aspect, etching of a hard mask beneath the photo-sensitive layer is performed after both of the first and second exposures.
摘要翻译：光刻方法使用不同的曝光模式。在一个方面，使用具有第一曝光图案（例如x-偶极图案）的光学器件，然后使用具有第二曝光图案的光学元件例如y型曝光，使用基板上的感光层进行第一次曝光，偶极图案，通过相同的掩模，并且光敏层相对于掩模固定。在一种方法中，可以使用157-193nm UV光和超数值孔径光学器件在光敏层下方的层中形成具有约70-150nm间距的2-D柱状图案。另一方面，在第一曝光和第二次曝光之后进行硬烘烤，以擦除在第一次曝光之后光致抗蚀剂的记忆效应。在另一方面，在第一和第二次曝光之后进行光敏层下面的硬掩模的蚀刻。

9. 发明申请

US20080160423A1 IMAGING POST STRUCTURES USING X AND Y DIPOLE OPTICS AND A SINGLE MASK 有权
标题翻译：使用X和Y DIPOLE OPTICS和单个掩模成像后结构
公开(公告)号：US20080160423A1
公开(公告)日：2008-07-03
申请号：US11618776
申请日：2006-12-30
申请人： Yung-Tin Chen , Steven J. Radigan , Paul Poon , Michael W. Konevecki
发明人： Yung-Tin Chen , Steven J. Radigan , Paul Poon , Michael W. Konevecki
IPC分类号： G03C5/00 , G03F1/00
CPC分类号： G03F7/70466 , G03F1/00 , G03F7/70425
摘要： A photolithographic method uses different exposure patterns. In one aspect, a photo-sensitive layer on a substrate is subject to a first exposure using optics having a first exposure pattern, such as an x-dipole pattern, followed by exposure using optics having a second exposure pattern, such as a y-dipole pattern, via the same mask, and with the photo-sensitive layer fixed relative to the mask. A 2-D post pattern with a pitch of approximately 70-150 nm may be formed in a layer beneath the photo-sensitive layer using 157-193 nm UV light, and hyper-numerical aperture optics, in one approach. In another aspect, hard baking is performed after both of the first and second exposures to erase a memory effect of photoresist after the first exposure. In another aspect, etching of a hard mask beneath the photo-sensitive layer is performed after both of the first and second exposures.
摘要翻译：光刻方法使用不同的曝光模式。在一个方面，使用具有第一曝光图案（例如x-偶极图案）的光学器件，然后使用具有第二曝光图案的光学元件例如y型曝光，使用基板上的感光层进行第一次曝光，偶极图案，通过相同的掩模，并且光敏层相对于掩模固定。在一种方法中，可以使用157-193nm UV光和超数值孔径光学器件在光敏层下方的层中形成具有约70-150nm间距的2-D柱状图案。另一方面，在第一曝光和第二次曝光之后进行硬烘烤，以擦除在第一次曝光之后光致抗蚀剂的记忆效应。在另一方面，在第一和第二次曝光之后进行光敏层下面的硬掩模的蚀刻。

10. 发明授权

US07994068B2 Method for fabricating a 3-D integrated circuit using a hard mask of silicon-oxynitride on amorphous carbon 有权
标题翻译：使用无定形碳上的氮氧化硅硬掩模制造3-D集成电路的方法
公开(公告)号：US07994068B2
公开(公告)日：2011-08-09
申请号：US12750596
申请日：2010-03-30
申请人： Steven J. Radigan , Michael W. Konevecki
发明人： Steven J. Radigan , Michael W. Konevecki
IPC分类号： H01L21/31
CPC分类号： H01L27/1021 , H01L23/5252 , H01L27/0688 , H01L29/8615 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a 3-D monolithic memory device. Silicon-oxynitride (SixOyNz) on amorphous carbon is used an effective, easily removable hard mask with high selectivity to silicon, oxide, and tungsten. A silicon-oxynitride layer is etched using a photoresist layer, and the resulting etched SixOyNz layer is used to etch an amorphous carbon layer. Silicon, oxide, and/or tungsten layers are etched using the amorphous carbon layer. In one implementation, conductive rails of the 3-D monolithic memory device are formed by etching an oxide layer such as silicon dioxide (SiO2) using the patterned amorphous carbon layer as a hard mask. Memory cell diodes are formed as pillars in polysilicon between the conductive rails by etching a polysilicon layer using another patterned amorphous carbon layer as a hard mask. Additional levels of conductive rails and memory cell diodes are formed similarly to build the 3-D monolithic memory device.
摘要翻译：一种用于制造3-D单片存储器件的方法。无定形碳上的氮氧化硅（SixOyNz）被用于对硅，氧化物和钨具有高选择性的有效的，容易移除的硬掩模。使用光致抗蚀剂层蚀刻硅 - 氧氮化物层，并且使用所得到的蚀刻的六方氮化物层来蚀刻无定形碳层。使用无定形碳层蚀刻硅，氧化物和/或钨层。在一个实施方案中，通过使用图案化的非晶碳层作为硬掩模来蚀刻诸如二氧化硅（SiO 2）的氧化物层来形成3-D单片存储器件的导电轨道。通过使用另一图案化的非晶碳层作为硬掩模蚀刻多晶硅层，在导电轨道之间的多晶硅中形成存储单元二极管。与构建3-D单片存储器件类似地形成附加电平的导电轨和存储单元二极管。

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