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1. 发明申请

US20100161902A1 METHOD, SYSTEM, AND PROGRAM FOR AN ADAPTOR TO READ AND WRITE TO SYSTEM MEMORY 有权
标题翻译：适用于读取和写入系统存储器的方法，系统和程序
公开(公告)号：US20100161902A1
公开(公告)日：2010-06-24
申请号：US12537987
申请日：2009-08-07
申请人： Michael Thomas Benhase , James Chien-Chung Chen , Yu-Cheng Hsu , Matthew Joseph Kalos , Carol Spanel , Andrew Dale Walls
发明人： Michael Thomas Benhase , James Chien-Chung Chen , Yu-Cheng Hsu , Matthew Joseph Kalos , Carol Spanel , Andrew Dale Walls
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0866 , G06F12/1081
摘要： Provided are a method, system, and program for an adaptor to read and write to system memory. A plurality of blocks of data to write to storage are received at an adaptor. The blocks of data are added to a buffer in the adaptor. A determination is made of pages in a memory device and I/O requests are generated to write the blocks in the buffer to the determined pages, wherein two I/O requests are generated to write to one block split between two pages in the memory device. The adaptor executes the generated I/O requests to write the blocks in the buffer to the determined pages in the memory device.
摘要翻译：提供了适配器读取和写入系统内存的方法，系统和程序。在适配器处接收要写入存储器的多个数据块。数据块被添加到适配器中的缓冲区。确定存储器设备中的页面并且生成I / O请求以将缓冲器中的块写入到所确定的页面，其中生成两个I / O请求以写入存储器设备中的两个页面之间的一个块分割。适配器执行生成的I / O请求，将缓冲区中的块写入存储器设备中确定的页面。

2. 发明授权

US08024524B2 Method, system, and program for an adaptor to read and write to system memory 有权
标题翻译：用于读取和写入系统内存的适配器的方法，系统和程序
公开(公告)号：US08024524B2
公开(公告)日：2011-09-20
申请号：US12537987
申请日：2009-08-07
申请人： Michael Thomas Benhase , James Chien-Chung Chen , Yu-Cheng Hsu , Matthew Joseph Kalos , Carol Spanel , Andrew Dale Walls
发明人： Michael Thomas Benhase , James Chien-Chung Chen , Yu-Cheng Hsu , Matthew Joseph Kalos , Carol Spanel , Andrew Dale Walls
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0866 , G06F12/1081
摘要： Provided are a method, system, and program for an adaptor to read and write to system memory. A plurality of blocks of data to write to storage are received at an adaptor. The blocks of data are added to a buffer in the adaptor. A determination is made of pages in a memory device and I/O requests are generated to write the blocks in the buffer to the determined pages, wherein two I/O requests are generated to write to one block split between two pages in the memory device. The adaptor executes the generated I/O requests to write the blocks in the buffer to the determined pages in the memory device.
摘要翻译：提供了适配器读取和写入系统内存的方法，系统和程序。在适配器处接收要写入存储器的多个数据块。数据块被添加到适配器中的缓冲区。确定存储器设备中的页面并且生成I / O请求以将缓冲器中的块写入到所确定的页面，其中生成两个I / O请求以写入存储器设备中的两个页面之间的一个块分割。适配器执行生成的I / O请求，将缓冲区中的块写入存储器设备中确定的页面。

3. 发明授权

US07627716B2 Method, system, and program for an adaptor to read and write to system memory 失效
标题翻译：用于读取和写入系统内存的适配器的方法，系统和程序
公开(公告)号：US07627716B2
公开(公告)日：2009-12-01
申请号：US10990039
申请日：2004-11-15
申请人： Michael Thomas Benhase , James Chien-Chiung Chen , Yu-Cheng Hsu , Matthew Joseph Kalos , Carol Spanel , Andrew Dale Walls
发明人： Michael Thomas Benhase , James Chien-Chiung Chen , Yu-Cheng Hsu , Matthew Joseph Kalos , Carol Spanel , Andrew Dale Walls
IPC分类号： G06F13/00 , G06F3/00
CPC分类号： G06F12/0866 , G06F12/1081
摘要： Provided are a method, system, and program for an adaptor to read and write to system memory. A plurality of blocks of data to write to storage are received at an adaptor. The blocks of data are added to a buffer in the adaptor. A determination is made of pages in a memory device and I/O requests are generated to write the blocks in the buffer to the determined pages, wherein two I/O requests are generated to write to one block split between two pages in the memory device. The adaptor executes the generated I/O requests to write the blocks in the buffer to the determined pages in the memory device.
摘要翻译：提供了适配器读取和写入系统内存的方法，系统和程序。在适配器处接收要写入存储器的多个数据块。数据块被添加到适配器中的缓冲区。确定存储器设备中的页面并且生成I / O请求以将缓冲器中的块写入到所确定的页面，其中生成两个I / O请求以写入存储器设备中的两个页面之间的一个块分割。适配器执行生成的I / O请求，将缓冲区中的块写入存储器设备中确定的页面。

4. 发明授权

US07870417B2 Apparatus, system, and method for adapter card failover 有权
标题翻译：适配卡故障切换的装置，系统和方法
公开(公告)号：US07870417B2
公开(公告)日：2011-01-11
申请号：US11738142
申请日：2007-04-20
申请人： Stephen L. Blinick , Cheng-Chung Song , Carol Spanel , Andrew Dale Walls
发明人： Stephen L. Blinick , Cheng-Chung Song , Carol Spanel , Andrew Dale Walls
IPC分类号： G06F11/00
CPC分类号： G06F11/2038 , G06F11/2033 , G06F11/2046
摘要： An apparatus, system, and method are disclosed for adapter card failover. A switch module connects a first processor complex to an adapter card through a first port as an owner processor complex. The owner processor complex manages the adapter card except for a second port and receives error messages from the adapter card. The switch module further connects a second processor complex to the adapter card through the second port as a non-owner processor complex. The non-owner processor complex manages the second port. A detection module detects a failure of the first processor complex. A setup module modifies the switch module to logically connect the second processor complex to the adapter card as the owner processor complex and to logically disconnect the first processor complex from the adapter card in response to detecting the failure.
摘要翻译：公开了用于适配器卡故障切换的装置，系统和方法。开关模块通过作为所有者处理器的第一端口将第一处理器复合体连接到适配器卡。所有者处理器复合体管理适配器卡，但第二个端口除外，并从适配器卡接收错误消息。交换机模块通过第二端口进一步将第二处理器复合体连接到适配器卡，作为非所有者处理器复合体。非所有者处理器复合体管理第二个端口。检测模块检测第一处理器复杂的故障。设置模块修改交换机模块以将所有者处理器复杂化，将第二处理器复合体逻辑连接到适配器卡，并根据检测到故障从逻辑上断开第一个处理器复合体与适配器卡的连接。

5. 发明申请

US20080301529A1 APPARATUS AND METHOD FOR DISTINGUISHING SINGLE BIT ERRORS IN MEMORY MODULES 有权
标题翻译：记忆模块中单位错误识别的装置和方法
公开(公告)号：US20080301529A1
公开(公告)日：2008-12-04
申请号：US11757162
申请日：2007-06-01
申请人： Carol Spanel , Andrew Dale Walls
发明人： Carol Spanel , Andrew Dale Walls
IPC分类号： G11C29/52
CPC分类号： G11C29/44 , G06F11/1012 , G11C5/04 , G11C29/52 , G11C2029/0409 , G11C2029/0411
摘要： An apparatus, system, and method are disclosed for distinguishing correctable bit errors in memory. A bit error detection module detects a correctable bit error in memory. The correctable bit error is correctable using error-correcting code (“ECC”). A comparison module compares an error location indicator with a stored error location indicator. The error location indicator is a location of the correctable bit error. The stored error location indicator includes to at least one previously stored error location indicator of a previously detected correctable bit error. A storage module stores the error location indicator in response to the comparison module determining that the error location indicator differs from a stored error location indicator. A bit error counter module increases a random bit error counter if the comparison module determines that the error location indicator differs from a stored error location indicator and does not increase the random bit error counter otherwise.
摘要翻译：公开了用于区分存储器中的可校正位错误的装置，系统和方法。位错误检测模块检测存储器中可纠正的位错误。使用纠错码（“ECC”）可纠正位错误。比较模块将错误位置指示器与存储的错误位置指示器进行比较。错误位置指示符是可纠正位错误的位置。存储的错误位置指示符包括至少一个先前存储的先前检测到的可校正位错误的错误位置指示符。存储模块响应于比较模块确定错误位置指示符与存储的错误位置指示符不同而存储错误位置指示符。如果比较模块确定错误位置指示符与存储的错误位置指示符不同，则错误计数器模块会增加随机位错误计数器，否则不会增加随机位错误计数器。

6. 发明授权

US08032816B2 Apparatus and method for distinguishing temporary and permanent errors in memory modules 失效
标题翻译：用于区分存储器模块中的临时和永久性错误的装置和方法
公开(公告)号：US08032816B2
公开(公告)日：2011-10-04
申请号：US11757221
申请日：2007-06-01
申请人： Carol Spanel , Andrew Dale Walls
发明人： Carol Spanel , Andrew Dale Walls
IPC分类号： G11C29/00
CPC分类号： G11C29/52 , G06F11/1012 , G11C5/04 , G11C29/44 , G11C2029/0409 , G11C2029/0411
摘要： An apparatus and method for distinguishing correctable bit errors in memory. A bit error detection module detects a correctable bit error in a memory in response to a READ operation. The correctable bit error is correctable using error-correcting code. The READ operation is generated during normal operation. A comparison module compares an error location indicator with a stored error location indicator. The error location indicator includes a memory location of the correctable bit error. The stored error location indicator corresponds to a previously stored error location indicator of a previous correctable bit error. A storage module stores the error location indicator if the comparison module determines that the error location indicator differs from a stored error location indicator. An error counter module increases an error counter corresponding to the error location indicator if the comparison module determines that the error location indicator matches a stored error location indicator.
摘要翻译：用于区分存储器中可校正位错误的装置和方法。响应于READ操作，位错误检测模块检测存储器中的可校正位错误。使用纠错码可纠正位错误。在正常操作期间产生READ操作。比较模块将错误位置指示器与存储的错误位置指示器进行比较。错误位置指示符包括可纠正位错误的存储位置。存储的错误位置指示符对应于先前存储的可纠错位错误的错误位置指示符。如果比较模块确定错误位置指示符与存储的错误位置指示符不同，则存储模块存储错误位置指示符。如果比较模块确定错误位置指示符与存储的错误位置指示符匹配，则错误计数器模块增加与错误位置指示符相对应的错误计数器。

7. 发明授权

US07971124B2 Apparatus and method for distinguishing single bit errors in memory modules 有权
标题翻译：用于区分存储器模块中的单个位错误的装置和方法
公开(公告)号：US07971124B2
公开(公告)日：2011-06-28
申请号：US11757162
申请日：2007-06-01
申请人： Carol Spanel , Andrew Dale Walls
发明人： Carol Spanel , Andrew Dale Walls
IPC分类号： G11C29/00
CPC分类号： G11C29/44 , G06F11/1012 , G11C5/04 , G11C29/52 , G11C2029/0409 , G11C2029/0411
摘要： An apparatus, system, and method are disclosed for distinguishing correctable bit errors in memory. A bit error detection module detects a correctable bit error in memory. The correctable bit error is correctable using error-correcting code (“ECC”). A comparison module compares an error location indicator with a stored error location indicator. The error location indicator is a location of the correctable bit error. The stored error location indicator includes to at least one previously stored error location indicator of a previously detected correctable bit error. A storage module stores the error location indicator in response to the comparison module determining that the error location indicator differs from a stored error location indicator. A bit error counter module increases a random bit error counter if the comparison module determines that the error location indicator differs from a stored error location indicator and does not increase the random bit error counter otherwise.
摘要翻译：公开了用于区分存储器中的可校正位错误的装置，系统和方法。位错误检测模块检测存储器中可纠正的位错误。使用纠错码（“ECC”）可纠正位错误。比较模块将错误位置指示器与存储的错误位置指示器进行比较。错误位置指示符是可纠正位错误的位置。存储的错误位置指示符包括至少一个先前存储的先前检测到的可校正位错误的错误位置指示符。存储模块响应于比较模块确定错误位置指示符与存储的错误位置指示符不同而存储错误位置指示符。如果比较模块确定错误位置指示符与存储的错误位置指示符不同，则错误计数器模块会增加随机位错误计数器，否则不会增加随机位错误计数器。

8. 发明授权

US07284153B2 Apparatus, method, and system for logging diagnostic information 有权
标题翻译：用于记录诊断信息的装置，方法和系统
公开(公告)号：US07284153B2
公开(公告)日：2007-10-16
申请号：US10715266
申请日：2003-11-17
申请人： Bitwoded Okbay , Carol Spanel , Andrew Dale Walls
发明人： Bitwoded Okbay , Carol Spanel , Andrew Dale Walls
IPC分类号： G06F11/00
CPC分类号： G06F11/3636 , G06F11/364
摘要： A diagnostic tracing logger is presented for use in a multithread environment in which diagnostic trace log entries are captured and recorded. The trace logs are composed of sequences of memory addresses used to access instructions and operands, instruction op-codes and register specifiers, sequences of memory addresses, branch instructions or exceptions, the contents of registers or semiconductor memory locations, and the like. In one embodiment, a software module configures a plurality of buffers to capture bus traces, each trace triggered by a specific pattern. A buffer controller manages transfer of diagnostic trace information from the plurality of buffers to a diagnostic log without using processor memory cycles. The trace information is transferred to a selected buffer using a processor cache flush instruction. Diagnostic trace logging facilitates diagnosis of complex system and software interactions without the cost and overhead of prior art trace logging techniques.
摘要翻译：呈现诊断跟踪记录器，用于在其中捕获和记录诊断跟踪日志条目的多线程环境中使用。跟踪日志由用于访问指令和操作数，指令操作码和寄存器说明符，存储器地址序列，分支指令或异常，寄存器或半导体存储器位置的内容等的存储器地址的序列组成。在一个实施例中，软件模块配置多个缓冲器以捕获总线迹线，每个跟踪由特定模式触发。缓冲器控制器管理诊断跟踪信息从多个缓冲器到诊断日志的传送，而不使用处理器存储器周期。使用处理器高速缓存刷新指令将跟踪信息传输到选定的缓冲区。诊断跟踪记录便于诊断复杂的系统和软件交互，而不需要现有技术跟踪记录技术的成本和开销。

9. 发明授权

US06496890B1 Bus hang prevention and recovery for data communication systems employing a shared bus interface with multiple bus masters 有权
标题翻译：采用与多个总线主机的共享总线接口的数据通信系统的总线挂起预防和恢复
公开(公告)号：US06496890B1
公开(公告)日：2002-12-17
申请号：US09454681
申请日：1999-12-03
申请人： Michael Joseph Azevedo , Brent Cameron Beardsley , Bitwoded Okbay , Carol Spanel , Andrew Dale Walls
发明人： Michael Joseph Azevedo , Brent Cameron Beardsley , Bitwoded Okbay , Carol Spanel , Andrew Dale Walls
IPC分类号： G06F1300
CPC分类号： G06F13/4036 , G06F13/28
摘要： A shared bus hang prevention and recovery scheme for a data communication system is provided, where a shared bus is connected to a plurality of bus masters and corresponding slaves and located between an external bus connected to a system processor, and an internal bus connected to an internal processor. Some of the masters are associated with the external bus and others are associated with the internal bus, and one of the bus masters is a control master associated with the internal processor. The scheme utilizes a shared bus hang prevention and recovery device having a circuitry and a control code. The circuitry is timing each pending request of the control master for the shared bus and initiating bus recovery if the shared bus is hung up, when the control master exceeded a pre-determined time period allowed for waiting to acquire the shared bus control and complete the transfer on the shared bus. The control code is used for monitoring and controlling the circuitry and terminating the transfer in progress causing the shared bus hang-up. During the bus recovery the circuitry prevents bus request grants to the master attached to the external bus until the master subsequent reset, and the control program instructions initiates transfers for all pending requests for the shared bus from the control master queue. Each transfer is being timed and terminated if the shared bus is hung up again. Upon the control master queue clearing, the internal processor executes the control program instructions to reset and reinitialize all masters and slaves on the shared bus.
摘要翻译：提供了一种用于数据通信系统的共享总线挂起预防和恢复方案，其中共享总线连接到多个总线主机和相应的从站，并且位于连接到系统处理器的外部总线与连接到系统处理器的内部总线之间内部处理器一些主机与外部总线相关，其他主机与内部总线相关，其中一个总线主机是与内部处理器相关的控制主机。该方案利用具有电路和控制码的共享总线挂起防止和恢复装置。如果控制主机超过了允许等待获取共享总线控制的预定时间段并且完成了共享总线控制并且完成在共享总线上传输。控制代码用于监视和控制电路，并终止正在进行的传输，从而导致共享总线挂断。在总线恢复期间，电路阻止对连接到外部总线的主机的总线请求授权，直到主机后续复位，并且控制程序指令从控制主机队列开始对所有未决请求的共享总线的传输。如果共享总线再次挂起，则每次传输都将被定时和终止。当控制主队列清除时，内部处理器执行控制程序指令，以复位和重新初始化共享总线上的所有主机和从机。

10. 发明申请

US20080301345A1 MULTI-CHARACTER ADAPTER CARD 失效
标题翻译：多字符适配卡
公开(公告)号：US20080301345A1
公开(公告)日：2008-12-04
申请号：US11754821
申请日：2007-05-29
申请人： Stephen L. Blinick , Carol Spanel , Andrew Dale Walls
发明人： Stephen L. Blinick , Carol Spanel , Andrew Dale Walls
IPC分类号： G06F13/00
CPC分类号： G06F13/385
摘要： One embodiment of an adapter card in accordance with the invention includes a circuit board connectable to a motherboard of a computer system. A logic chip is connected to the circuit board to provide functionality to the adapter card. One or more programmable devices are connected to the circuit board and store data read by the logic chip upon initialization. This data may include first character data to program the logic chip to have a first character and second character data to program the logic chip to have a second character. A switching mechanism is provided to switch between the first and second character data in response to an external input, thereby causing the logic chip to read one of the first and second character data.
摘要翻译：根据本发明的适配器卡的一个实施例包括可连接到计算机系统的主板的电路板。逻辑芯片连接到电路板以向适配器卡提供功能。一个或多个可编程设备连接到电路板，并在初始化时存储由逻辑芯片读取的数据。该数据可以包括用于对逻辑芯片编程以具有第一字符和第二字符数据的第一字符数据，以将逻辑芯片编程为具有第二字符。提供切换机制以响应于外部输入在第一和第二字符数据之间切换，从而使逻辑芯片读取第一和第二字符数据之一。

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